Advanced Pheripheral Bus design using verilog HDL
-
Updated
Sep 7, 2021 - Verilog
Advanced Pheripheral Bus design using verilog HDL
Design of a system bus architecture - Team Project @ ENTC UoM
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Add a description, image, and links to the amba-apb topic page so that developers can more easily learn about it.
To associate your repository with the amba-apb topic, visit your repo's landing page and select "manage topics."