instruction-set-architecture

Star

Here are 124 public repositories matching this topic...

hlorenzi / customasm

Sponsor

Star

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Updated Jan 20, 2024
Rust

Maratyszcza / Opcodes

Star

Database of CPU Opcodes

x86-64 instructions x86 opcodes instruction-set-architecture

Updated Feb 18, 2024
Python

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Star

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

gabrieldim / Assembly-MIPS-Instruction-Set

Star

Assembly program with the MIPS instruction set

mips assembly mips-assembly assembly-language instruction-set-architecture

Updated Dec 23, 2020
Assembly

edanor / umesimd

Star

UME::SIMD A library for explicit simd vectorization.

Updated Jan 19, 2018
C++

scarv / xcrypto

Star

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

AluVM / rust-aluvm

Star

Rust implementation of AluVM (RISC functional machine)

rust microcontrollers functional-programming virtual-machine smart-contracts blockchain embedded-systems risc instruction-set-architecture edge-computing

Updated Apr 28, 2024
Rust

mikeroyal / AMX-Guide

Star

Advanced Matrix Extensions (AMX) Guide

awesome cpu fpga accelerator intel awesome-list amx instruction-set-architecture dsa awesome-resources datastreaming awesome-readme tilematrixset advancedmatrixextensions

Updated Jan 11, 2022
C++

kcelebi / riscv-assembler

Star

RISC-V Assembly code assembler package for Python.

python assembly-language-programming instruction-set-architecture risc-v riscv-assembler

Updated Apr 11, 2023
Python

TomerAberbach / mano-simulator

Sponsor

Star

🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

Updated May 26, 2023
Java

sjohann81 / hf-risc

Star

HF-RISC SoC

mips processor embedded-systems computer-architecture soc instruction-set-architecture risc-v instruction-set-simulator mpsoc hf-risc

Updated Apr 10, 2024
C

alirezakay / RISC-CPU

Star

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

scarv / scarv-cpu

Star

SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Jan 11, 2023
Verilog

sdasgup3 / parallel-processor-design

Star

Super scalar Processor design

Updated Sep 7, 2014
Verilog

dmjio / LC3

Sponsor

Star

💾 The LC3 virtual machine

haskell virtual-machine assembly opcodes lc3 instruction-set-architecture

Updated Jul 21, 2022
Haskell

katamaran-project / katamaran

Star

Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.

verification symbolic-execution instruction-set-architecture separation-logic