Super scalar Processor design
-
Updated
Sep 7, 2014 - Verilog
Super scalar Processor design
Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.
Superscalar OoO RISCV processor written in Chisel
Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang
A superscalar processor in Python
Out of order superscalar processor simulated in Javascript
A compiler, assembler, and processor.
MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support
A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
32-bit Superscalar RISC-V CPU
Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
CS-470 Homework 1
DUTH RISC-V Superscalar Microprocessor
Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Add a description, image, and links to the superscalar topic page so that developers can more easily learn about it.
To associate your repository with the superscalar topic, visit your repo's landing page and select "manage topics."