An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
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Updated
Apr 29, 2024 - Verilog
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terasic-de0
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Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
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Updated
Nov 14, 2020 - VHDL
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