Help understanding routing methods

[codefreak472]

I'm having trouble understanding the difference between the net.connect() method, and the net.addPin() method. The documentation for net.connect() states that it "Makes both logical and physical connections (EDIFNet and Net) for a logical pin on the given cell.", while net.addPin states that it "Adds a new pin to the net". But what does the latter mean? If a pin is added to a net, is it considered routed? Is it connected? Do connected and routed even mean the same thing? Should I be using one of these methods to connect static nets to pins? Or should I be using the Cell.connectStaticSourceToPin() method?

Additionally, Vivado has an option to connect multiple pins to multiple nets at once. the TCL for this is
connect_net -net_object_list <pin1 net1 pin2 net2 ...>

Does rapidwright have a method that does this? or should I just be using one of the aforementioned methods in a loop?

[clavin-xlnx]

My apologies for the late response. Let me try to answer your questions:

I'm having trouble understanding the difference between the net.connect() method, and the net.addPin() method. The documentation for net.connect() states that it "Makes both logical and physical connections (EDIFNet and Net) for a logical pin on the given cell.", while net.addPin states that it "Adds a new pin to the net". But what does the latter mean?

RapidWright (and correspondingly, Vivado) has two views of an implemented FPGA design. There is a logical netlist and a physical netlist. The logical netlist is essentially the design representation after the synthesis of RTL and does not usually contain placement or routing information. It is a graph of logical primitives (LUTs, flip-flops, carry elements, etc) connected by nets and defined in cell instances that may or may not be hierarchical in nature. In RapidWright, we use the com.xilinx.rapidwright.edif package and most classes prefixed with EDIF to represent parts of a logical netlist. For more info, see http://www.rapidwright.io/docs/RapidWright_Overview.html#edif-package-logical-netlist.

The physical netlist in RapidWright is the mapping of the logical netlist onto the device model. It contains placement information such as where a flip-flop should be placed (e.g. SLICE_X10Y10/AFF) and how routes should be routed. Routing is categorized into two types:

1. Intra-site routing (routing that describes connections inside of a site, i.e.BELPin to BELPin)
2. Inter-site routing (routing that describes connections outside of a site, i.e. SitePinInst to SitePinInst)

Placement data and intra-site routing is mostly captured in the SiteInst and Cell objects in a Design. Inter-site routing is captured in the Net objects. (see http://www.rapidwright.io/docs/RapidWright_Overview.html#design-package-physical-netlist for more details on the physical netlist).

Given that context, Net.connect() and Net.addPin() perform similar tasks, but the scope is different. The Net.connect() method is a convenience method that attempts to automate a few steps for you. In order for two pins on a cell to be connected, they need to belong to the same (or equivalent) logical net that describes connectivity and a physical net that describes (or will describe) the routing (or physical implementation of the connection). It is an error for two pins to be connected physically without a corresponding logical path. The Net.connect() method ensures that a logical net exists (creates an EDIFNet if one doesn't already exist) when connecting two pins before they are connected physically. The Net.addPin() connects a physical pin (SitePinInst) to a Net. It doesn't create any logical nets connection, this is implicitly assumed.

If a pin is added to a net, is it considered routed? Is it connected? Do connected and routed even mean the same thing?

If a pin is connected to a net, it would be considered "connected." It is not necessarily considered routed unless there exists a routed path already specified. Routed and connected are not the same thing. Generally, a routing step is required to route nets that have been connected or had their connectivity changed.

Should I be using one of these methods to connect static nets to pins? Or should I be using the Cell.connectStaticSourceToPin() method?

In theory, you could use either methods, but Cell.connectStaticSourceToPin() is probably the easiest as it will ensure that there is a logical source for the static net in the cell instance where you are connecting the pin. Again, this is a requirement to have the logical portion of the design in harmony with the physical portion of the design.

Additionally, Vivado has an option to connect multiple pins to multiple nets at once. the TCL for this is connect_net -net_object_list <pin1 net1 pin2 net2 ...>

Does rapidwright have a method that does this? or should I just be using one of the aforementioned methods in a loop?

RapidWright does have the API Net.addPins() where if you pass it a list of SitePinInst objects, it will add them all to the net such that they will all be connected.

I hope that helps, reach out if you have more questions.

[codefreak472]

that helps a lot. Thank you for such a thorough response!

[codefreak472]

In theory, you could use either methods, but Cell.connectStaticSourceToPin() is probably the easiest as it will ensure that there is a logical source for the static net in the cell instance where you are connecting the pin.

What does it mean to have a logical source for a static net? I thought static nets were physical, not logical.

Generally, a routing step is required to route nets that have been connected or had their connectivity changed.

Is this something I can do in rapidWright on a per route basis? I've seen the Design.routeSites() method, and the SiteInst.routeIntrasiteNet() method. Are there others I have overlooked?

One last question: when you have an inverter (SitePIP) in front of a cell pin, does this change how you connect the net to the cell pin?

Sorry for bombarding you with questions. Also, since that last question is only semi-related I can delete it and ask it in a new thread if you like. Thank you again for your help.

[clavin-xlnx]

What does it mean to have a logical source for a static net? I thought static nets were physical, not logical.

Static nets have both a physical representation (GLOBAL_LOGIC0 or GLOBAL_LOGIC1) and a logical representation (often called <const0> or <const1> on nets in cell instances). For example, there is a logical cell instance called GND and VCC that exist as a source in every cell instance throughout a netlist. You can see it listed in the netlist view on the left side of the Vivado screenshot below:

The schematic viewer doesn't exactly draw a box with a single output, instead it uses conventional schematic symbols, the GND source is highlighted in green in the schematic view on the right.

Looking at the physical implementation of the net corresponding to GND, we can see that Vivado highlights any and all nets that belong to GND (again, highlighted in green):

One interesting difference is that a logical static net will only have a single, localized source because it generally does not exit a cell instance. However, the physical static net for a design implementation will typically have many physical sources (as shown above). The physical static net is essentially the union of all the logical static nets of the same sense (GND or VCC) throughout the design.

Is this something I can do in rapidWright on a per route basis? I've seen the Design.routeSites() method, and the SiteInst.routeIntrasiteNet() method. Are there others I have overlooked?

Typically, routing nets is done all at once because it is faster and more efficient. Routing nets one at a time is certainly do-able, but not necessarily feasible. The two methods you cite are for routing the intra-site portion of nets (the routing inside of a site). This is typically completed before the final routing (inter-site routing) during or after placement.

There are a couple full design routers (inter-site routing) in RapidWright for routing a group of nets (or all nets). The most robust and performant is called RWRoute (see tutorials here: http://www.rapidwright.io/docs/RWRoute_timing_driven_routing.html, http://www.rapidwright.io/docs/RWRoute_wirelength_driven_routing.html, and http://www.rapidwright.io/docs/RWRoute_partial_routing.html).

One last question: when you have an inverter (SitePIP) in front of a cell pin, does this change how you connect the net to the cell pin?

Inverters are routing BELs (RBELs) and typically, the inversion is programmable based on the context. If your circuit requires GND at the input of the cell pin, the inverter is generally enabled by routing VCC to its input (VCC is much more plentiful in the device than GND). Otherwise, the inverter is not activated and signals are just passed through.