Verilog RTL design projects

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com

Arun Raja Manjini

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
16x1mux_TB.v		16x1mux_TB.v
Intr_controller.pdf		Intr_controller.pdf
README.md		README.md
SR_latch.v		SR_latch.v
SR_latch_TB.v		SR_latch_TB.v
beh_upcounter.v		beh_upcounter.v
clock_gen.v		clock_gen.v
encoder.v		encoder.v
memory_fr.v		memory_fr.v
mux.v		mux.v
mux_and.v		mux_and.v
shift_register.v		shift_register.v
shift_register_TB.v		shift_register_TB.v
tb_memory_fr.v		tb_memory_fr.v
tb_mux_and.v		tb_mux_and.v
tb_p_encoder.v		tb_p_encoder.v
tb_upcounter.v		tb_upcounter.v

aaronrjmanj/verilog

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Verilog RTL design projects

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