Repurposing existing HDL tools to help writing better code

A JSON library implemented in VHDL.

Portable HyperRAM controller

RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

Modelsim QEMU Unicorn integration via the FLI

A Python-based IP Core Management Infrastructure.

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Collection of scripts for EDA tools

Utilities for Avalon Memory Map

⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…

Latest addition to REPO : Folder with vending machine design and TB including code coverage report

Попытка написать несколько примеров кода на языке SystemVerilog.

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com

SublimeLinter plugin for linting VHDL with Modelsim vcom

UART IP-core for FPGA.