Calculator with music project written using Verilog in Xilinx Vivado targeting the Basys3 FPGA Board

Ping Pong Game in VHDL

Command line utilities for GHDL+vivado project management and simulation

vivado design to test the skidbuffer IP

RTL Final Project A.Y. 2020-2021

Reconfigurable Computing 1 Projects

C++ Data Structure with Vitis

ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.

100 days of RTL

This program implements a traffic light state machine on the Basys 3 development board. The traffic light consist of a RED, YELLOW and GREEN LEDs for the car lights and a RED and GREEN LEDs for the pedestrian ligths.

Logic Analyzer IP Core

Continuous integration environments for FPGAedu projects

A joystick-controlled Tetris game designed for a Zybo FPGA.

FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project

AXI stream protocol checking design

TCL script to run the whole process from project creation to bitstream writing to FPGA device in Xilinx Vivado.

Helloworld with Vitis on bare metal (standalone single-core)

Resolución de laboratorios y guías prácticas asignadas en el curso de Diseño Digital Avanzado 2022.

2110363 Hardware Synthesis Lab I (2022/1) - Term Project

Verilog Code for basic Operations