vivado
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Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts
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Nov 23, 2021 - Tcl
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Sep 25, 2023 - Tcl
Resolución de laboratorios y guías prácticas asignadas en el curso de Diseño Digital Avanzado 2022.
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Sep 25, 2022 - Jupyter Notebook
Docker container containing the Vitis 2023.2 tools & PetaLinux
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Apr 8, 2024 - Dockerfile
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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May 4, 2024 - SystemVerilog
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
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Dec 12, 2022 - VHDL
language server and vim plugin for xilinx vivado and vitis
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May 13, 2024 - Vim Script
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