riscV.vcd

$date
	Sun Feb  9 14:36:19 2020
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module branch_test $end
$scope module TB $end
$scope module top_inst $end
$var wire 1 ! clk $end
$var wire 1 " rst_n $end
$var wire 4 # write_transfer [3:0] $end
$var wire 1 $ we_mem_data $end
$var wire 32 % val_mem_prog [31:0] $end
$var wire 32 & val_mem_data_write [31:0] $end
$var wire 32 ' val_mem_data_read [31:0] $end
$var wire 10 ( addr_mem_prog [9:0] $end
$var wire 10 ) addr_mem_data [9:0] $end
$scope module core_inst $end
$var wire 1 ! clk $end
$var wire 1 " rst_n $end
$var wire 4 * write_transfer_mem_data_o [3:0] $end
$var wire 1 + we_reg_file $end
$var wire 1 $ we_mem_data_o $end
$var wire 32 , val_mem_prog_i [31:0] $end
$var wire 32 - val_mem_data_write_o [31:0] $end
$var wire 32 . val_mem_data_read_i [31:0] $end
$var wire 32 / rs2_reg_file [31:0] $end
$var wire 32 0 rs1_reg_file [31:0] $end
$var wire 5 1 r_num_write_reg_file [4:0] $end
$var wire 5 2 r2_num_read_reg_file [4:0] $end
$var wire 5 3 r1_num_read_reg_file [4:0] $end
$var wire 32 4 pc [31:0] $end
$var wire 32 5 new_pc [31:0] $end
$var wire 1 6 is_conditional_t $end
$var wire 1 7 is_branch_t $end
$var wire 32 8 imm_val_t [31:0] $end
$var wire 2 9 data_target_t [1:0] $end
$var wire 2 : data_origin_t [1:0] $end
$var wire 32 ; data_in_reg_file [31:0] $end
$var wire 32 < csr_val_w [31:0] $end
$var wire 32 = csr_val_r [31:0] $end
$var wire 3 > csr_op_t [2:0] $end
$var wire 12 ? csr_addr_t [11:0] $end
$var wire 10 @ addr_mem_prog_o [9:0] $end
$var wire 10 A addr_mem_data_o [9:0] $end
$var wire 3 B LIS_op_t [2:0] $end
$var wire 2 C BR_op_t [1:0] $end
$var wire 4 D ALU_op_t [3:0] $end
$scope module controlUnit_inst $end
$var wire 32 E instruction [31:0] $end
$var reg 4 F ALU_op [3:0] $end
$var reg 2 G BR_op_o [1:0] $end
$var reg 3 H LIS_op [2:0] $end
$var reg 12 I csr_addr_o [11:0] $end
$var reg 32 J csr_data_o [31:0] $end
$var reg 3 K csr_op_o [2:0] $end
$var reg 2 L data_origin_o [1:0] $end
$var reg 2 M data_target_o [1:0] $end
$var reg 3 N funct3 [2:0] $end
$var reg 7 O funct7 [6:0] $end
$var reg 12 P imm12 [11:0] $end
$var reg 12 Q imm12b [11:0] $end
$var reg 12 R imm12s [11:0] $end
$var reg 20 S imm20 [19:0] $end
$var reg 20 T imm20j [19:0] $end
$var reg 32 U imm_val_o [31:0] $end
$var reg 1 7 is_branch_o $end
$var reg 1 6 is_conditional_o $end
$var reg 1 V is_load_store $end
$var reg 1 $ mem_w $end
$var reg 7 W opcode [6:0] $end
$var reg 5 X r1_addr [4:0] $end
$var reg 5 Y r2_addr [4:0] $end
$var reg 5 Z rd [4:0] $end
$var reg 5 [ reg_addr [4:0] $end
$var reg 1 + reg_w $end
$var reg 5 \ rs1 [4:0] $end
$var reg 5 ] rs2 [4:0] $end
$var reg 4 ^ write_transfer_o [3:0] $end
$upscope $end
$scope module crs_unit_inst $end
$var wire 1 ! clk $end
$var wire 12 _ csr_addr_i [11:0] $end
$var wire 3 ` csr_op_i [2:0] $end
$var wire 32 a csr_val_i [31:0] $end
$var wire 1 " rst_n $end
$var wire 64 b timer_val_i [63:0] $end
$var reg 32 c csr_val_o [31:0] $end
$var reg 64 d timer_val_o [63:0] $end
$var reg 1 e timer_we_o $end
$scope module timer_inst $end
$var wire 1 ! clk $end
$var wire 1 " rst_n $end
$var wire 64 f val_i [63:0] $end
$var wire 1 e we_i $end
$var reg 64 g val_o [63:0] $end
$upscope $end
$upscope $end
$scope module exec_unit_inst $end
$var wire 4 h ALU_op [3:0] $end
$var wire 2 i BR_op [1:0] $end
$var wire 3 j LIS_op [2:0] $end
$var wire 32 k csr_val_i [31:0] $end
$var wire 2 l data_origin_i [1:0] $end
$var wire 2 m data_target_i [1:0] $end
$var wire 32 n imm_val_i [31:0] $end
$var wire 1 7 is_branch_i $end
$var wire 1 6 is_conditional_i $end
$var wire 1 o zero_alu_result $end
$var wire 32 p val_mem_data_write_o [31:0] $end
$var wire 32 q val_mem_data_read_i [31:0] $end
$var wire 32 r rs2_i [31:0] $end
$var wire 32 s rs1_i [31:0] $end
$var wire 32 t pc_i [31:0] $end
$var wire 32 u pc_4 [31:0] $end
$var wire 32 v new_pc_offset_o [31:0] $end
$var wire 32 w mem_o [31:0] $end
$var wire 32 x alu_o [31:0] $end
$var wire 10 y addr_mem_data_o [9:0] $end
$var reg 32 z d_o [31:0] $end
$var reg 32 { s1_ALU [31:0] $end
$var reg 32 | s2_ALU [31:0] $end
$scope module ALU $end
$var wire 4 } ALU_op [3:0] $end
$var wire 32 ~ s1 [31:0] $end
$var wire 32 !" s2 [31:0] $end
$var wire 1 o zero_o $end
$var wire 5 "" shift [4:0] $end
$var reg 32 #" d [31:0] $end
$upscope $end
$scope module BR $end
$var wire 1 o ALU_zero_i $end
$var wire 2 $" BR_op_i [1:0] $end
$var wire 32 %" alu_d [31:0] $end
$var wire 32 &" imm_i [31:0] $end
$var wire 1 7 is_branch_i $end
$var wire 1 6 is_conditional_i $end
$var wire 32 '" pc_4_o [31:0] $end
$var wire 32 (" pc_i [31:0] $end
$var wire 32 )" new_pc [31:0] $end
$var reg 32 *" new_pc_o [31:0] $end
$var reg 32 +" offset [31:0] $end
$upscope $end
$scope module LIS $end
$var wire 3 ," LIS_op [2:0] $end
$var wire 32 -" addr_mem_i [31:0] $end
$var wire 32 ." val_mem_write_i [31:0] $end
$var wire 32 /" val_mem_read_i [31:0] $end
$var wire 10 0" addr_mem_o [9:0] $end
$var reg 32 1" val_mem_read_o [31:0] $end
$var reg 32 2" val_mem_write_o [31:0] $end
$upscope $end
$upscope $end
$scope module program_counter_inst $end
$var wire 1 ! clk $end
$var wire 32 3" new_pc_i [31:0] $end
$var wire 1 " rst_n $end
$var reg 32 4" pc [31:0] $end
$upscope $end
$scope module reg_file_inst $end
$var wire 1 ! clk $end
$var wire 32 5" data_in [31:0] $end
$var wire 5 6" r1_num_read [4:0] $end
$var wire 5 7" r2_num_read [4:0] $end
$var wire 5 8" r_num_write [4:0] $end
$var wire 1 " rst_n $end
$var wire 1 + we $end
$var wire 32 9" rs2 [31:0] $end
$var wire 32 :" rs1 [31:0] $end
$scope begin REG $end
$var integer 32 ;" j [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module mem_data_inst $end
$var wire 10 <" addr [9:0] $end
$var wire 1 ! clk $end
$var wire 32 =" data_in [31:0] $end
$var wire 1 " rst_n $end
$var wire 1 $ we $end
$var wire 4 >" write_transfer_i [3:0] $end
$var wire 32 ?" data_out [31:0] $end
$scope begin MEM_WRITE $end
$var integer 32 @" j [31:0] $end
$upscope $end
$upscope $end
$scope module mem_prog_inst $end
$var wire 10 A" addr [9:0] $end
$var wire 1 ! clk $end
$var wire 32 B" data_out [31:0] $end
$var wire 1 " rst_n $end
$scope begin MEM_READ $end
$var integer 32 C" j [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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bx k
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$end
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