Originally a school assignment. It required an SRAM layout and circuit files used to optimize bitlines and transistors (only for all the other supporting componenets because SRAM transistor size was a constraint) for maximum performance and minimal space occupied. Used a 50nm CMOS model from CMOSedu.com.
Constraints: Only metal 1 and 2 were allowed for the design of the SRAM cell along with connections to VDD, GND, and write lines. Metal 3 was for the bitlines and of course N-well and P-well connections had to be made to the appropriate VDD and GND lines. The transistors also had to be 5x2 lambda.
The test circuit files were for testing the different componenets of the SRAM module in a SPICE simulator (I used LTspice) where I had to optimize the size for these different componenets and dummy loads were used to simulate the capacitive and resistive load that would normally be there without actually having to implement them to save time on the project.
Ultimatly due to time constraints a majority of the work was done on optimizing SRAM bitline widths and SRAM layout including how the cells would be placed (1x256, 2x128, 4x64, 8x32 or 16x16) which of course had an effect on how thin of a bitline you could get away with while maintaining good reads and writes and could aid in getting a more closely packed SRAM module.