Nuvoton: Fix FPGA CI test failing #11152

ccli8 · 2019-08-02T02:56:14Z

Description

This PR is to pass FPGA CI test shield tests on Nuvoton targets. It has the following major bugfix:

Skip some Nuvoton targets not supporting pull-up/pull-down input mode
Force enum PinName to 32-bit required to encode module binding information in it
Exclude USB UART from testing which is dedicated to USB VCOM
Fix IP initialization sequence
Fix I2C NACK error
Fix redundant SPI clock generation
Fix redundant call to UART IRQ handler
Support GPIO input pull-high/pull-low (not all Nuvoton targets support it)
Other target-specific bugfix

Pull request type

[X] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change

ciarmcom · 2019-08-02T03:00:30Z

@ccli8, thank you for your changes.
@Ronny-Liu @ARMmbed/mbed-os-maintainers @ARMmbed/mbed-os-test @ARMmbed/mbed-os-hal please review.

SeppoTakalo · 2019-08-05T12:47:18Z

@ccli8 Please fix that Astyle error.
Seems to be just one whitespace problem.

ccli8 · 2019-08-06T01:51:34Z

Make the following modifications:

Do rebase
Fix astyle
Remove FPGA: Skip Nuvoton targets for SPI 4-bit symbol size test because master has removed 4/12-bit symbol size test
Exclude A2/A3 from testing for NuMaker-IoT-M487 V1.3 board

0xc0170 · 2019-08-08T09:41:40Z

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp

+    // Some targets don't support pull-up/pull-down mode.
+#if !defined(TARGET_NANO100) &&         \
+    !defined(TARGET_NUC472) &&          \
+    !defined(TARGET_M451)


How can we eliminate these if target. Is this functionality a must ? Can we check differently if this mode is supported?

Having this ifdef is not ideal, means we are testing something is not either supported by all targets or we are missing a check to ask for "is this supported, test it".

Check gpio_mode(...) and pin_mode(...) but find no spec on the mode parameter. It seems most targets support PullDown/PullUp input pull mode. However, old-chip based Nuvoton targets like above don't support it. And there's no configuration option to disable it.

void gpio_mode(gpio_t *obj, PinMode mode); void pin_mode(PinName pin, PinMode mode);

@ARMmbed/mbed-os-hal Does this look correct as it is?

@ccli8 The whole // Test input, pull-up mode. should be excluded if these targets do not support pull-up mode.

How can we eliminate these if target. Is this functionality a must ? Can we check differently if this mode is supported?

Having this ifdef is not ideal, means we are testing something is not either supported by all targets or we are missing a check to ask for "is this supported, test it".

Frankly, I didn't expect any target that does not support pull-up/pull-down modes. The only thing that comes to my mind, to make this a bit more readable, is to define a new macro in targets.json file. That could be either "GPIO_PINMODE" in "device_has" section or "GPIO_PINMODE_NOT_SUPPORTED" in "macros". @ccli8, @0xc0170, @OPpuolitaival, what do you think?

Before that, I think the mode parameter should be well defined. It just allows PullNone/PullUp/PullDown, or it can also allow other modes like target-specific? Only meaningful for input mode?

void gpio_mode(gpio_t *obj, PinMode mode); void pin_mode(PinName pin, PinMode mode);

fkjagodzinski · 2019-08-19T10:38:48Z

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp

+    // Some targets don't support pull-up/pull-down mode.
+#if !defined(TARGET_NANO100) &&         \
+    !defined(TARGET_NUC472) &&          \
+    !defined(TARGET_M451)


@ccli8 The whole // Test input, pull-up mode. should be excluded if these targets do not support pull-up mode.

fkjagodzinski · 2019-08-19T10:40:40Z

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp


    // Test input, pull-down mode.
    gpio_mode(&gpio, PullDown);
    tester.gpio_write(MbedTester::LogicalPinGPIO0, 0, false);
    wait_us(HI_Z_READ_DELAY_US);
+    // Some targets don't support pull-up/pull-down mode.


Same as above -- the whole // Test input, pull-down mode. should be excluded if pull-down is not supported.

@fkjagodzinski Including above, fixed as commented

Thanks for a quick update. Don't you think the #if statement is a bit too wide now? I thought that only the pull-up and pull-down modes are unsupported; pull-none was OK, wasn't it? I'd rather see these lines enclosed in #if !defined(TARGET_NANO100) .... I do not have these targets available for local tests, so will let you decide. 😉

@fkjagodzinski Chip may have fixed (non-configurable) input pull mode on these targets. To be not confusing, pull modes (PullNone/PullUp/PullDown) are not supported on these targets.

In that case, we can leave the #if statements as they are.

fkjagodzinski · 2019-08-19T10:44:44Z

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp

+    // Some targets don't support pull-up/pull-down mode.
+#if !defined(TARGET_NANO100) &&         \
+    !defined(TARGET_NUC472) &&          \
+    !defined(TARGET_M451)


Since every step of this test (test_explicit_input()) sets one of the PinModes, the whole test should be skipped if not supported. I think the #if statement should be moved to the declaration of cases below.

@fkjagodzinski Fixed as commented

…n mode The Nuvoton targets listed below don't support input pull-up/pull-down mode and so are skipped for test: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453

The most suitable place to free up I2C pins is in i2c_free(). Due to i2c_free() not available in I2C HAL, we free up I2C pins manually by configuring them back to GPIO. Without free-up of I2C pins, SDA/SCL pins of the same I2C peripheral may share by multiple ports due to 'all ports' tests here, and the following I2C tests would be subject to interference by shared ports.

NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it.

USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.

Better IP initialization sequence: 1. Configure IP pins 2. Select IP clock source and then enable it 3. Reset the IP (SYS_ResetModule) NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if IP clock enable is before IP reset. NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then IP reset. NOTE3: IP reset at the end of IP initialization sequence can cover unexpected situation.

Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API.

Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.

Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.

In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453

Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference.

MOSI1/MISO1 are used in second bit of 2-bit transfer mode and cannot be used for normal MOSI/MISO. Remove them from pinmap. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - basic test.

M451 series can classify by M45xD/M45xC and M45xG/M45xE. To support this classification: 1. Create TARGET_M45xD_M45xC and TARGET_M45xG_M45xE targets. 2. Mark NUMAKER_PFM_M453 belongs to TARGET_M45xG_M45xE by 'extra_labels_add' in targets.json. 3. Fix pin name table according to the classification. 4. Fix pinmap table according to the classification.

Fix SPI module index error in modidx_ns_tab table in CLK_SetModuleClock_S(). Need to update secure image for this bugfix. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - init/free test all pins.

Since NuMaker-IoT-M487 V1.3, A2/A3 are dedicated to on-board ESP8266 WiFi module RTS/CTS pins and so must exclude from FPGA CI testing.

0xc0170

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp change still needs to be approved by @fkjagodzinski

fkjagodzinski · 2019-08-20T10:25:13Z

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp change still needs to be approved by @fkjagodzinski

I've just left one last comment to consider.

ccli8 · 2019-08-22T10:26:33Z

@fkjagodzinski @0xc0170 Any update?

0xc0170 · 2019-08-22T12:24:18Z

CI started

mbed-ci · 2019-08-22T16:33:03Z

Test run: SUCCESS

Summary: 11 of 11 test jobs passed
Build number : 1
Build artifacts

adbridge · 2019-08-23T10:20:09Z

This is sitting on top of 5.14 code so now targeting 5.14 instead

ciarmcom requested review from Ronny-Liu and a team August 2, 2019 03:00

ciarmcom added the needs: review label Aug 2, 2019

ccli8 force-pushed the nuvoton_fpga-ci branch from 475a64f to e8c2210 Compare August 6, 2019 01:46

ccli8 force-pushed the nuvoton_fpga-ci branch from 8f4a551 to 5539954 Compare August 6, 2019 09:35

0xc0170 requested changes Aug 8, 2019

View reviewed changes

fkjagodzinski suggested changes Aug 19, 2019

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ccli8 force-pushed the nuvoton_fpga-ci branch from 5539954 to 2d93f50 Compare August 20, 2019 03:50

ccli8 added 15 commits August 20, 2019 13:12

FPGA: Skip some Nuvoton targets not supporting input pull-up/pull-dow…

0e09260

…n mode The Nuvoton targets listed below don't support input pull-up/pull-down mode and so are skipped for test: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453

[Nuvoton] Force enum PinName to 32-bit

f88bd72

NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it.

[Nuvoton] Exclude USB UART from testing

560fe33

USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.

[Nuvoton] Fix I2C NACK error

80c21ae

Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API.

[Nuvoton] Fix redundant SPI clock generation

d46c6fe

Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.

[Nuvoton] Fix redundant call to UART IRQ handler

09bf844

Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.

[Nuvoton] Support GPIO input pull-high/pull-low

ca0846b

In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453

[Nuvoton] Free up peripheral pins in peripheral free-up HAL API

c3d7ef8

Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference.

[NANO130] Remove SPI MOSI1/MISO1 pins from pinmap

6f1bd32

MOSI1/MISO1 are used in second bit of 2-bit transfer mode and cannot be used for normal MOSI/MISO. Remove them from pinmap. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - basic test.

[M2351] Fix CLK_SetModuleClock_S(...) error with SPI

07f39f1

Fix SPI module index error in modidx_ns_tab table in CLK_SetModuleClock_S(). Need to update secure image for this bugfix. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - init/free test all pins.

[M2351] Fix pinmap table error with SPI clock pin

c99c43c

[M487] Exclude A2/A3 from testing for NuMaker-IoT-M487 V1.3

96dac4f

Since NuMaker-IoT-M487 V1.3, A2/A3 are dedicated to on-board ESP8266 WiFi module RTS/CTS pins and so must exclude from FPGA CI testing.

ccli8 force-pushed the nuvoton_fpga-ci branch from 2d93f50 to 96dac4f Compare August 20, 2019 05:13

0xc0170 self-requested a review August 20, 2019 09:57

0xc0170 approved these changes Aug 20, 2019

View reviewed changes

0xc0170 added needs: work and removed needs: review labels Aug 20, 2019

fkjagodzinski approved these changes Aug 22, 2019

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0xc0170 added needs: CI and removed needs: work labels Aug 22, 2019

adbridge added the release-version: 5.13.4 label Aug 22, 2019

0xc0170 merged commit 48b5939 into ARMmbed:master Aug 23, 2019

0xc0170 removed the needs: CI label Aug 23, 2019

adbridge added release-version: 5.14.0-rc1 and removed release-version: 5.13.4 labels Aug 23, 2019

ccli8 mentioned this pull request Aug 30, 2019

M263: Fix FPGA CI testing failing #11379

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Nuvoton: Fix FPGA CI test failing #11152

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Nuvoton: Fix FPGA CI test failing #11152

Nuvoton: Fix FPGA CI test failing #11152

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