Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
Nuvoton: Fix FPGA CI test failing #11152
This PR is to pass FPGA CI test shield tests on Nuvoton targets. It has the following major bugfix:
Pull request type
…n mode The Nuvoton targets listed below don't support input pull-up/pull-down mode and so are skipped for test: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453
The most suitable place to free up I2C pins is in i2c_free(). Due to i2c_free() not available in I2C HAL, we free up I2C pins manually by configuring them back to GPIO. Without free-up of I2C pins, SDA/SCL pins of the same I2C peripheral may share by multiple ports due to 'all ports' tests here, and the following I2C tests would be subject to interference by shared ports.
NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it.
Better IP initialization sequence: 1. Configure IP pins 2. Select IP clock source and then enable it 3. Reset the IP (SYS_ResetModule) NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if IP clock enable is before IP reset. NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then IP reset. NOTE3: IP reset at the end of IP initialization sequence can cover unexpected situation.
Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API.
Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.
Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453
MOSI1/MISO1 are used in second bit of 2-bit transfer mode and cannot be used for normal MOSI/MISO. Remove them from pinmap. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - basic test.
M451 series can classify by M45xD/M45xC and M45xG/M45xE. To support this classification: 1. Create TARGET_M45xD_M45xC and TARGET_M45xG_M45xE targets. 2. Mark NUMAKER_PFM_M453 belongs to TARGET_M45xG_M45xE by 'extra_labels_add' in targets.json. 3. Fix pin name table according to the classification. 4. Fix pinmap table according to the classification.
Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference.
Fix SPI module index error in modidx_ns_tab table in CLK_SetModuleClock_S(). Need to update secure image for this bugfix. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - init/free test all pins.
0xc0170 merged commit
Aug 23, 2019
25 checks passed
25 checks passed
continuous-integration/jenkins/pr-head This commit looks goodDetails
jenkins-ci/dynamic-memory-usage RTOS ROM(+0 bytes) RAM(-24 bytes)Details
travis-ci/events Success! Runtime is 8524 cycles.Details
travis-ci/littlefs Success! Code size is 8464B.Details
Add this suggestion to a batch that can be applied as a single commit. This suggestion is invalid because no changes were made to the code. Suggestions cannot be applied while the pull request is closed. Suggestions cannot be applied while viewing a subset of changes. Only one suggestion per line can be applied in a batch. Add this suggestion to a batch that can be applied as a single commit. Applying suggestions on deleted lines is not supported. You must change the existing code in this line in order to create a valid suggestion. Outdated suggestions cannot be applied. This suggestion has been applied or marked resolved. Suggestions cannot be applied from pending reviews.