Add CYW9P62S1_43012EVB_01 board

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

@@ -82,7 +82,7 @@
 #include "S25FL512S_config.h"
 
 #elif   defined(TARGET_CYW9P62S1_43012EVB_01)
-#include "S25FS128S_config.h"
+#include "S25FS512S_config.h"
 
 #elif   defined(TARGET_CY8CPROTO_064_SB)
 #include "S25FL128S_config.h"

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,34 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+	init_cycfg_system();
+	init_cycfg_clocks();
+	init_cycfg_routing();
+	init_cycfg_peripherals();
+	init_cycfg_pins();
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,47 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,90 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,71 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_USB_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 3U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 4U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+
+#endif /* CYCFG_NOTICES_H */