STM32WB RNG: enable use from both M4 and M0+ cores

[jeromecoutant]

Summary of changes

When M0+ CPU with BLE and M4 CPU with MBED application are using both RNG feature,
there was some conflict in clock configuration.

Now, M4 CPU is set as the master.

Fix #13145

@ARMmbed/team-st-mcd
@eriknayan

Impact of changes

This enables RNG use in MBED application in parallel of BLE.

This could also improve USB use as USB is sharing the same clock as RNG in STM32WB

Migration actions required

Documentation

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Pull request type

[x] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

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Test results

[] No Tests required for this change (E.g docs only update)
[x] Covered by existing mbed-os tests (Greentea or Unittest)
[] Tests / results supplied as part of this PR

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Reviewers

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[LMESTM]

This is a generic way indeed to restart all the clocks. But it can take time and have impacts on power consumption. What is actually missing at this point, is it only HSI48 ?
if so, isn't it enough to call again :

while` (LL_HSEM_1StepLock(HSEM, CFG_HW_HSI48_SEMID));

of course that's an optimization only

[jeromecoutant]

Idea was to ease maintenance.
If we change something in SetSysClock, it will be automatically taken into account at STOP mode exit.

[0xc0170]

But it can take time and have impacts on power consumption.

what we are losing here ? Any numbers?

[jeromecoutant]

But it can take time and have impacts on power consumption.
what we are losing here ? Any numbers?

No measure, but I don't think this takes more time than switching only HSI48 clock here.

[ciarmcom]

@jeromecoutant, thank you for your changes.
@ARMmbed/mbed-os-maintainers please review.

[0xc0170]

CI started

[mbed-ci]

Test run: SUCCESS

Summary: 6 of 6 test jobs passed
Build number : 1
Build artifacts

[eriknayan]

Thanks @jeromecoutant for this patch!