Add memory barriers to STM32F7xx Ethernet #5720
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@ARMmbed/team-st-mcd please review |
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/morph build |
Build : SUCCESSBuild number : 713 Triggering tests/morph test |
Exporter Build : FAILUREBuild number : 364 |
Test : SUCCESSBuild number : 542 |
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/morph export-build |
Exporter Build : SUCCESSBuild number : 367 |
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This will be ready once travis fix is landed, will need to be rebased to get the travis fix propagated. |
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@kjbracey-arm Can you rebase (travis fix to get in to resolve the failure), I'll restart Ci asap |
Pending official update from STM, add memory barriers to the Ethernet HAL code for the STM32F7xx family. Cortex-M7 has a merging write buffer that is not automatically flushed by accesses to devices, so without these DMBs, we sometimes lose synch with the transmitter. The DMBs are architecturally needed in every version of this HAL, but adding just to the STM32F7 version for now to clear test, as the problem has only been observed on Cortex-M7-based devices. Fixes ARMmbed#5622.
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Rebased. |
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/morph build |
Build : SUCCESSBuild number : 727 Triggering tests/morph test |
Exporter Build : SUCCESSBuild number : 378 |
Test : FAILUREBuild number : 556 |
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@kjbracey-arm The latest test result reports one failure for k64f ARM: |
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Need to have few rounds to see if it fixes the issue /morph test |
Test : SUCCESSBuild number : 559 |
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Not sure if multiple CI successes on this PR should raise confidence - the observation was that the success rate was either near 0% or near 100% for a specific image, and the theory was that depends on alignment of the transmit buffers in the image. I'd expect you to get the same result on every test, whether or not this was fixing it. If I could see that the image being tested had the transmit buffers at a +0x1c offset, or if current tip of master was failing, I'd be semi-convinced. On the K64F thing starting to be visible (#5680) - have we just started testing debug images? Or has the network segment they're on just gotten busier? I'll figure out a patch for it. |
ghost
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Hi |
haven't seen it on master. I restarted also build phase in the referenced PR, will wait for results |
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Would that need to be rebased? Does the build test PR tip or merge result? |
CI merges with master, but we triggered only test phase (build was old one as I noticed), so I restarted the build as well |
Pending official update from STM, add memory barriers to the Ethernet
HAL code for the STM32F7xx family.
Cortex-M7 has a merging write buffer that is not automatically flushed
by accesses to devices, so without these DMBs, we sometimes lose synch
with the transmitter.
The DMBs are architecturally needed in every version of this HAL, but
adding just to the STM32F7 version for now to clear test, as the
problem has only been observed on Cortex-M7-based devices.
Fixes #5622.