Skip to content
View Abdulwadoodd's full-sized avatar
🎯
Focusing
🎯
Focusing

Organizations

@openhwgroup @10x-Engineers @riscv-admin @ee-uet
Block or Report

Block or report Abdulwadoodd

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. LumosRV LumosRV Public

    Implementation of 5-stage pipelined RISC-V processor - RV32I - in Verilog

    Verilog

  2. cocotb cocotb Public

    Forked from cocotb/cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    Python

  3. serv serv Public

    Forked from olofk/serv

    SERV - The SErial RISC-V CPU

    Verilog 1

  4. pcie-crd pcie-crd Public

    State Machine of Current Running Disparity calculator for PCI express physical layer

    Verilog 1

  5. blinky blinky Public

    Forked from fusesoc/blinky

    Example LED blinking project for your FPGA dev board of choice

    Tcl

  6. sail-riscv sail-riscv Public

    Forked from riscv/sail-riscv

    Sail RISC-V model

    Coq