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Table of Content

  1. HES


HES™ is a SoC/ASIC pre-silicon prototyping solution for hardware verification and software validation teams and the High Performance Computing (HPC) platform for algorithms acceleration. The boards are based on largest Virtex-7 and Virtex UltraScale FPGA and appear in single or multi-FPGA configurations and can be interconnected on a backplane board providing up to 663 Million ASIC gates.

Aldec provides the following list of boards:

Link to the HES boards page

Vivado - board definition files

Vivado board definition files contain configuration of FPGAs available on the board to simplify using the Aldec HES board in Xilinx Vivado tool.

The board definition files for HES boards can be found in Vivado-board_files folder.

The board definition files are provided for the following Aldec HES boards:

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