Skip to content
View AleksandarLilic's full-sized avatar
Block or Report

Block or report AleksandarLilic

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. ama-riscv ama-riscv Public

    Verilog implementation of RISC-V RV32I ISA

    Verilog

  2. AES-256_UVM AES-256_UVM Public

    UVM testbench for AES-256 VHDL design

    SystemVerilog

  3. ama-riscv-sim ama-riscv-sim Public

    Instruction Set Simulator for RISC-V RV32I in C++

    C++

  4. AES-256_hardware_design AES-256_hardware_design Public

    VHDL design of the AES-256 encryption algorithm

    VHDL 1 1

  5. Cyclone_II_SoPC Cyclone_II_SoPC Public

    VHDL hardware accelerators on Cyclone II FPGA with MCU apps in C for Nios II core

    C 3

  6. LPC1768_development LPC1768_development Public

    CMSIS-RTOS2, driver development and data acquisition application on NXP LPC1768

    C 2