Docente: Prof. Gianluca Palermo
Studenti:
- Andrea Riva (matricola: 887449)
- Alessandro Sanvito (matricola: 891196)
The aim of the project was the specification in VHDL of a computer architecture able to decode an 8-bit memory address encoded with the so-called "working zones" method. The "working zones" approach tries to leverage data locality to reduce energy consumption while reducing the memory footprint of addresses. We then tested the architecture in the Vivado Testbench to assess its formal correctness. The resulting architecture is optimized for speed.
Final mark: 30/30 cum laude