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Ver 0.1.2 #7

Merged
merged 11 commits into from
Oct 14, 2023
16 changes: 0 additions & 16 deletions .github/workflows/release.yml
Original file line number Diff line number Diff line change
Expand Up @@ -2,25 +2,9 @@ name: Release

on:
push:
branches:
- master
paths:
- Cargo.toml
tags:
- "v*.*.*"

jobs:
tag:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
fetch-depth: 2
- uses: salsify/action-detect-and-tag-new-version@v2
id: detect_tag
with:
create-tag: true
version-command: cargo read-manifest | jq -r .version
build:
runs-on: ubuntu-latest
steps:
Expand Down
21 changes: 21 additions & 0 deletions .github/workflows/tag.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
name: Tag

on:
push:
branches:
- master
paths:
- Cargo.toml

jobs:
tag:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
fetch-depth: 2
- uses: salsify/action-detect-and-tag-new-version@v2
id: detect_tag
with:
create-tag: true
version-command: cargo read-manifest | jq -r .version
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "raki"
version = "0.1.1"
version = "0.1.2"
edition = "2021"
authors = ["Norimasa Takana <alignof@outlook.com>"]
description = "RISC-V instruction decoder written in Rust."
Expand Down
4 changes: 2 additions & 2 deletions src/decode/inst_16.rs
Original file line number Diff line number Diff line change
Expand Up @@ -118,8 +118,8 @@ mod decode_16 {
);
test_16(0x4521, C_LI, Some(10), None, None, Some(8));
test_16(0xb5e5, C_J, None, None, None, Some(-280));
test_16(0x6105, C_ADDI, None, Some(2), None, Some(32));
test_16(0x8082, C_JR, None, Some(1), None, None);
test_16(0x6105, C_ADDI, Some(2), Some(2), None, Some(32));
test_16(0x8082, C_JR, None, Some(1), Some(0), None);
test_16(0xe29d, C_BNEZ, None, Some(13), None, Some(38));
test_16(0xc05c, C_SW, None, Some(8), Some(15), Some(4));
test_16(0x9002, C_EBREAK, None, None, None, None);
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18 changes: 11 additions & 7 deletions src/decode/inst_16/c_extension.rs
Original file line number Diff line number Diff line change
Expand Up @@ -126,15 +126,16 @@ pub fn parse_rd(inst: u16, opkind: &OpcodeKind) -> Result<Option<usize>, Decodin
| OpcodeKind::C_AND
| OpcodeKind::C_ADDW
| OpcodeKind::C_SUBW => Ok(Some(q1_rd)),
OpcodeKind::C_LI | OpcodeKind::C_LUI | OpcodeKind::C_ADDI | OpcodeKind::C_ADDIW => {
Ok(Some(q1_wide_rd))
}
OpcodeKind::C_LI
| OpcodeKind::C_LUI
| OpcodeKind::C_ADDI
| OpcodeKind::C_ADDIW
| OpcodeKind::C_ADDI16SP => Ok(Some(q1_wide_rd)),
// Quadrant 2
OpcodeKind::C_SLLI
| OpcodeKind::C_LWSP
| OpcodeKind::C_LDSP
| OpcodeKind::C_MV
| OpcodeKind::C_JALR
| OpcodeKind::C_ADD => Ok(Some(q2_rd)),
_ => Ok(None),
}
Expand Down Expand Up @@ -190,9 +191,12 @@ pub fn parse_rs2(inst: u16, opkind: &OpcodeKind) -> Result<Option<usize>, Decodi
| OpcodeKind::C_SUBW
| OpcodeKind::C_ADDW => Ok(Some(q1_rs2)),
// Quadrant 2
OpcodeKind::C_MV | OpcodeKind::C_ADD | OpcodeKind::C_SWSP | OpcodeKind::C_SDSP => {
Ok(Some(q2_rs2))
}
OpcodeKind::C_JR
| OpcodeKind::C_JALR
| OpcodeKind::C_MV
| OpcodeKind::C_ADD
| OpcodeKind::C_SWSP
| OpcodeKind::C_SDSP => Ok(Some(q2_rs2)),
_ => Ok(None),
}
}
Expand Down
17 changes: 8 additions & 9 deletions src/decode/inst_32/zicsr_extension.rs
Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,8 @@ pub fn parse_rs1(inst: u32, opkind: &OpcodeKind) -> Result<Option<usize>, Decodi

// LUI, AUIPC, JAL, FENCE, ECALL, EBREAK
match opkind {
OpcodeKind::CSRRW
| OpcodeKind::CSRRS
| OpcodeKind::CSRRC
| OpcodeKind::CSRRWI
| OpcodeKind::CSRRSI
| OpcodeKind::CSRRCI => Ok(Some(rs1)),
_ => panic!("This instruction does not have rs1"),
OpcodeKind::CSRRW | OpcodeKind::CSRRS | OpcodeKind::CSRRC => Ok(Some(rs1)),
_ => Ok(None),
}
}

Expand All @@ -62,6 +57,10 @@ pub fn parse_rs2(inst: u32, opkind: &OpcodeKind) -> Result<Option<usize>, Decodi
}
}

pub fn parse_imm(_inst: u32, _opkind: &OpcodeKind) -> Result<Option<i32>, DecodingError> {
Ok(None)
pub fn parse_imm(inst: u32, opkind: &OpcodeKind) -> Result<Option<i32>, DecodingError> {
let uimm: i32 = inst.slice(19, 15) as i32;
match opkind {
OpcodeKind::CSRRWI | OpcodeKind::CSRRSI | OpcodeKind::CSRRCI => Ok(Some(uimm)),
_ => Ok(None),
}
}
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