v2.0 Automated Testbench

The testbench is now automated and more exhaustive by using assembly files as the testcases. Multiple bugs were discovered by the automated testbench and is now fixed.

Fix

• Casted operator a to $signed() for SRA(shift right arithmetic) operation of ALU
• Added logic for choosing which byte/halfword to be loaded to basereg in LB(load byte) and LH(load halfword) instruction
• Converted reg sum to wire in rv32i_writeback since it's always equating to zero due to the blocking assignment
• Initialized all basereg to zero to avoid error in testbench (e.g. addi instruction loads value to 12 LSBs but since the 24 MSBs are still X(unknown) when basereg is not initialized, the ALU operation fails)

New

• test.sh = shell script for automating the testbench
• sections.py = python script used by test.sh to extract the text and data sections from the binary file output of the compiler
• testbank/ = assembly testfiles for all 37 basic instructions with RISC-V International's riscv-tests pass/fail criteria