Fix some issues in the RV32F extension implementation #27
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Can you run |
I don't mind but the formatting issues are not only in my code . To avoid the "bloat" in the diff, should I just make another formatting PR ? |
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yeah would probably be a useful PR |
adutilleul
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Jun 28, 2023
This PR introduces some changes needed to support the handling of floating point operations (F extension) in the `riscv` dialect and all the operations themselves, which is necessary for future works. The main points are: - Split the class `RegisterType` into two different classes to distinguish between integer and floating point registers. This is handy when register allocating and also to ensure the soundness of the dialect in order to stay in line with the ISA. Thus, the user has to specify directly the type of the register when using it inside an operation (`riscv.ireg` or `riscv.freg`). - I'm still unsure if that's the best way of doing this, so I'm open to suggestions. - I've updated already most of the test suite, including the emulation tests, where I found some issues in the `riscemu` library which resulted in a PR (AntonLydike/riscemu#27), still pending to be merged.
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Some instructions in the RV32F extension didn't have the right behavior or had some type errors. I fixed what I needed right now but I didn't do a thorough check of all the instructions.