dialects: (riscv) add initial support for F extension #1188
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## main #1188 +/- ##
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- Coverage 88.96% 88.71% -0.26%
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Files 166 166
Lines 22551 22855 +304
Branches 3404 3478 +74
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+ Hits 20062 20275 +213
- Misses 1945 2025 +80
- Partials 544 555 +11
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One thing to consider is to keep the integer register "Register" and add the floating point as "FloatingPointRegister", since integer registers is what we'll be using the most by far, and they're the only ones in the core spec |
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I have cleaned up the PR a bit to keep a smaller diff by applying the suggestion of @superlopuh. |
adutilleul
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adutilleul
changed the title
xdsl/dialects/riscv.py
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| @@ -1396,7 +1513,7 @@ class BltuOp(RsRsOffOperation): | |||
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| @irdl_op_definition | |||
| class BgeuOp(RsRsOffOperation): | |||
| class BgeuOp(RsRsOffOperationInteger): | |||
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This either appears are ...OperationInteger or ...IntegerOperation.
Is this on purpose? Shouldn't both be the latter?
xdsl/dialects/riscv.py
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| @irdl_attr_definition | ||
| class FloatingRegisterType(Data[Register], TypeAttribute): |
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sorry for being pedantic, but can you use Float instead of Floating?
I want to remember one mnemonic if possible :)
| @@ -25,6 +25,7 @@ def module(): | |||
| seven = riscv.LiOp(7).rd | |||
| forty_two = riscv.MulOp(six, seven).rd | |||
| riscv.CustomAssemblyInstructionOp("print", inputs=[forty_two], result_types=[]) | |||
| riscv.ReturnOp() | |||
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I think this was added in another PR, can you rebase/merge please?
This PR introduces some changes needed to support the handling of floating point operations (F extension) in the
riscvdialect and all the operations themselves, which is necessary for future works.The main points are:
RegisterTypeinto two different classes to distinguish betweeninteger and floating point registers. This is handy when register allocating and
also to ensure the soundness of the dialect in order to stay in line with the ISA.
Thus, the user has to specify directly the type of the register when using it inside
an operation (
riscv.iregorriscv.freg).riscemulibrary which resulted in a PR (Fix some issues in the RV32F extension implementation AntonLydike/riscemu#27), still pending to be merged.