Set DSR and CTS (etc) according to serial TCP connection state

[sicklittlemonkey]

From Rémy GIBERT:
Something else in the same area that should be more an enhancement than a bug fix, but,
is it possible to set DSR and CTS lines low when TCP connection is established, and high when TCP connection is dropped?

Cheers,
Nick.

[tomcw]

is it possible to set DSR and CTS lines low when TCP connection is established, and high when TCP connection is dropped?

DSR: see #386, and can be tested with AppleWin 1.26.3.0 onwards.
CTS/RTS (Clear To Send/Request To Send): Maybe instead this is DCD/DTR - see #386 (and again AppleWin 1.26.3.0).

Since I think these signals are now supported, I'm now closing this issue.

[tomcw]

NB. To get AppleWin to emulate the DTR, DCD and DSR signals then you must use the -modem switch (see History.txt in the zip release).

[tomcw]

Actually CTS is read by reading SSC's DIPSW2 register, eg. at $C0A2 (for SSC in slot-2). Bit0 is CTS, and is true when 0. See SSC manual, page-54.

This isn't currently supported in AppleWin, so I'm reopening this issue.

[tomcw]

NB. RTS (Request to Send). The state of this pin in determined by the contents of the Command register (Ref: SY6551 datasheet).

[burniouf]

The idea behind is to get the information that the link is broken....so either RTS/CTS.....or ....DCD....DSR/DTR.....whatever....

just to be clear : i mean when the "Serial Port" is set to "TCP"
DCD could be fine to relate the TCP "Established" State....

[tomcw]

NB. From csa2, "Where is Turbo ASB add on Card for the Super Serial Card ??", (here) XRR references this Turbo ASB doc, which says:

"... It’s also worth noting that the original 6551 ACIA has a bug which causes problems with ‘Hardware Handshaking’ (aka – CTS Hardware Flow Control). Although the entire Turbo ASB module isn’t needed to fix this bug, just the new 65C51 IC is."

And from this page:

A note should be made here regarding CTS and the 6551. An applications note I have here for the Synertek NMOS 6551, as well as the '87 Rockwell data book's NMOS 6551 pages say that transmission of an already-started frame will stop immediately when CTS is taken false, the byte will be lost, and the TD line will go to marking. I consider this to be either a serious bug, or an idiotic part of the original NMOS design. The same Rockwell book says that the CMOS 65c51 will finish the already-started byte before halting transmission after CTS goes false. (IOW, they corrected that problem when they did the CMOS design.) The other data sheets I have only say CTS must be true for the ACIA to transmit, without giving details of what happens when CTS is taken false in the middle of a frame. My expectation then is that regardless of brand, the CMOS ones generally will finish the frame whereas the NMOS ones won't.

[tomcw]

New AppleWin 1.27.2.0 build here.