flop adder fertig

Arseni · Jun 10, 2012 · ab00e18 · ab00e18
1 parent e5adf3f
commit ab00e18
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Showing 3 changed files with 33 additions and 17 deletions.
diff --git a/flop.v b/flop.v
@@ -26,7 +26,7 @@ module flop
 
 reg signBig, signSmall, signResult;
 reg [3:0] expBig, expSmall, expDiff, normalizer, expResult;
-reg [7:0] mantBig, mantSmall, mantSmallAligned, mantResult;
+reg [7:0] mantBig, mantSmall, mantSmallAligned, mantSumNorm, mantResult;
 reg [8:0] mantSum;
 
 always @*
@@ -35,19 +35,19 @@ begin
 	begin
 		signBig = one[12];
 		signSmall = other[12];
-		expBig = one [11:4];
-		expSmall = other[11:4];
-		mantBig = one[3:0];
-		mantSmall = other[3:0];
+		mantBig = one [11:4];
+		mantSmall = other[11:4];
+		expBig = one[3:0];
+		expSmall = other[3:0];
 	end
 	else
 	begin
 		signBig = other[12];
 		signSmall = one[12];
-		expBig = other[11:4];
-		expSmall = one[11:4];
-		mantBig = other[3:0];
-		mantSmall = one[3:0];
+		mantBig = other[11:4];
+		mantSmall = one[11:4];
+		expBig = other[3:0];
+		expSmall = one[3:0];
 	end
 
 	expDiff = expBig - expSmall;
@@ -66,10 +66,24 @@ begin
 				 mantSum[1] ? 'o6 :
 				 'o7;
 
-	mantResult = mantSum << normalizer;
-	expResult = mantSum[8] ? 
-					expBig - normalizer + 1:
-					expBig - normalizer;
+	mantSumNorm	= mantSum[7:0] << normalizer;
+
+	if(mantSum[8])
+	begin
+		expResult = expBig + 1;
+		mantResult = mantSum[8:1];
+	end
+	else if (normalizer > expBig)
+	begin
+		expResult = 0;
+		mantResult = 0;
+	end
+	else
+	begin
+		expResult = expBig - normalizer;
+		mantResult = mantSumNorm;
+	end
+
 	signResult = signBig == signSmall ? 1 : signBig;
 
 	result = {signResult, mantResult, expResult};

diff --git a/nexys3.xise b/nexys3.xise
@@ -17,11 +17,13 @@
   <files>
     <file xil_pn:name="sseg.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="sseg_display.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="sseg_test.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -41,7 +43,7 @@
     </file>
     <file xil_pn:name="flop.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="flop_test.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>

diff --git a/sseg_display.v b/sseg_display.v
@@ -22,7 +22,7 @@ module sseg_display
 (
 	input rst,
 	input clk,
-	input wire [7:0] value,
+	input wire [12:0] value,
 	output wire [3:0] sseg_an,
 	output wire [7:0] sseg_sig
 );