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0 parents commit c143b792dc8b5a7aa5812f300fbd7074298ea453 @Arseni committed May 29, 2012
Showing with 38 additions and 0 deletions.
  1. +38 −0 nexys3.xise
38 nexys3.xise
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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+
+ <files>
+</files>
+
+ <properties>
+ <property xil_pn:name="Project Description" xil_pn:value=""/>
+ <property xil_pn:name="Working Directory" xil_pn:value="C:/xilinxProjects/nexys3"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values"/>
+ <property xil_pn:name="Manual Compile Order" xil_pn:value="false"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+
+</project>

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