Hardware Chasing Leds

In this project the number displayed on the seven-segment display must be in decimal, the slide switches 0 to 7 as the delay input (J15 to R13), slide switch 15 as a stop signal (V10) and BTND as the reset button. Also the longest delay at 255 should be around 500 mS and the shortest delay at 000 should be around 50 mS

This project includes:

1. midterm.src code sources,
   1. Main modules include delayed_led and m_counter module, along with modules to drive the 7-segment and thus all system.
2. 500ms Simulation
3. 50ms Simulation with reset
4. Simulation with diffrent inputs, a reset and stop
5. Initial schematic using draw.io
6. Vivado Block diagram
7. Youtube video of the system implementation using the FPGA board
   Click here for project video