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Right now RSQRTSS encoded with opcode F3 0F 52 use operand type ss for its operand of addressing W which is defined as:
Scalar element of a 128-bit packed single-precision floating data.
According to the intel docs:
Computes an approximate reciprocal of the square root of the low single-precision floating-point value in the source operand (second operand) stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register.
Since it's only operate on the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type d which is defined as:
Doubleword, regardless of operand-size attribute.
The text was updated successfully, but these errors were encountered:
Kashio
added a commit
to Kashio/x86reference
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this issue
Jan 14, 2023
Right now
RSQRTSS
encoded with opcodeF3 0F 52
use operand typess
for its operand of addressingW
which is defined as:According to the intel docs:
Since it's only operate on the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type
d
which is defined as:The text was updated successfully, but these errors were encountered: