CMPSS use wrong operand types

[Kashio]

Right now CMPSS encoded with opcode F3 0F C2 use operand type ss for its operand of addressing W which is defined as:

Scalar element of a 128-bit packed single-precision floating data.

According to the intel docs:

Compare low single-precision floating-point value in
xmm2/m32 and xmm1 using bits 2:0 of imm8 as
comparison predicate.

Since it's only comparing the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type q which is defined as:

Doubleword, regardless of operand-size attribute.

[BarebitOpenSource]

This one looks right. Refer to #23.

[BarebitOpenSource]

Feel free to reopen this issue if you still think the operand type is wrong.