Create example4.evcd #52
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The example is retrieved from 1800-2017 IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language 21.7.4.4 Extended VCD file format example (pp. 671-672). The example omits $date, $version, $comment, $timescale, etc. because their syntaxe is the same for VCD and EVCD. The timestamps are changed to small numbers to help demonstration.
Ben1152000
approved these changes
Aug 26, 2022
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The example is retrieved from 1800-2017 IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language 21.7.4.4 Extended VCD file format example (pp. 671-672). The example omits $date, $version, $comment, $timescale, etc. because their syntaxe is the same for VCD and EVCD. The timestamps are changed to small numbers to help demonstration.