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schematics and component placement ready for review.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,198 @@ | ||
| update=26.02.2019 15:42:42 | ||
| version=1 | ||
| last_client=kicad | ||
| [general] | ||
| version=1 | ||
| RootSch= | ||
| BoardNm= | ||
| [cvpcb] | ||
| version=1 | ||
| NetIExt=net | ||
| [eeschema] | ||
| version=1 | ||
| LibDir= | ||
| [eeschema/libraries] | ||
| [schematic_editor] | ||
| version=1 | ||
| PageLayoutDescrFile= | ||
| PlotDirectoryName=../schematic/ | ||
| SubpartIdSeparator=0 | ||
| SubpartFirstId=65 | ||
| NetFmtName= | ||
| SpiceAjustPassiveValues=0 | ||
| LabSize=50 | ||
| ERC_TestSimilarLabels=1 | ||
| [pcbnew] | ||
| version=1 | ||
| PageLayoutDescrFile= | ||
| LastNetListRead= | ||
| CopperLayerCount=8 | ||
| BoardThickness=1.6 | ||
| AllowMicroVias=0 | ||
| AllowBlindVias=0 | ||
| RequireCourtyardDefinitions=0 | ||
| ProhibitOverlappingCourtyards=1 | ||
| MinTrackWidth=0.102 | ||
| MinViaDiameter=0.35 | ||
| MinViaDrill=0.152 | ||
| MinMicroViaDiameter=0.35 | ||
| MinMicroViaDrill=0.127 | ||
| MinHoleToHole=0.0254 | ||
| TrackWidth1=0.102 | ||
| TrackWidth2=0.112 | ||
| TrackWidth3=0.118 | ||
| TrackWidth4=0.127 | ||
| TrackWidth5=0.15 | ||
| TrackWidth6=0.178 | ||
| TrackWidth7=0.254 | ||
| TrackWidth8=0.4 | ||
| ViaDiameter1=0.35 | ||
| ViaDrill1=0.152 | ||
| ViaDiameter2=0.35 | ||
| ViaDrill2=0.152 | ||
| ViaDiameter3=0.35 | ||
| ViaDrill3=0.152 | ||
| ViaDiameter4=0.6 | ||
| ViaDrill4=0.35 | ||
| dPairWidth1=0.2 | ||
| dPairGap1=0.25 | ||
| dPairViaGap1=0.25 | ||
| dPairWidth2=0.102 | ||
| dPairGap2=0.22 | ||
| dPairViaGap2=0.22 | ||
| dPairWidth3=0.112 | ||
| dPairGap3=0.22 | ||
| dPairViaGap3=0.22 | ||
| SilkLineWidth=0.15 | ||
| SilkTextSizeV=0.5 | ||
| SilkTextSizeH=0.5 | ||
| SilkTextSizeThickness=0.09999999999999999 | ||
| SilkTextItalic=0 | ||
| SilkTextUpright=1 | ||
| CopperLineWidth=0.09999999999999999 | ||
| CopperTextSizeV=1.5 | ||
| CopperTextSizeH=1.5 | ||
| CopperTextThickness=0.3 | ||
| CopperTextItalic=0 | ||
| CopperTextUpright=1 | ||
| EdgeCutLineWidth=0.09999999999999999 | ||
| CourtyardLineWidth=0.05 | ||
| OthersLineWidth=0.15 | ||
| OthersTextSizeV=1 | ||
| OthersTextSizeH=1 | ||
| OthersTextSizeThickness=0.15 | ||
| OthersTextItalic=0 | ||
| OthersTextUpright=1 | ||
| SolderMaskClearance=0 | ||
| SolderMaskMinWidth=0.25 | ||
| SolderPasteClearance=0 | ||
| SolderPasteRatio=-0 | ||
| [pcbnew/Layer.In1.Cu] | ||
| Name=In1.Cu | ||
| Type=1 | ||
| [pcbnew/Layer.In3.Cu] | ||
| Name=In3.Cu | ||
| Type=1 | ||
| [pcbnew/Layer.In6.Cu] | ||
| Name=In6.Cu | ||
| Type=1 | ||
| [pcbnew/Netclasses] | ||
| [pcbnew/Netclasses/1] | ||
| Name=DDR | ||
| Clearance=0.1 | ||
| TrackWidth=0.127 | ||
| ViaDiameter=0.35 | ||
| ViaDrill=0.152 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/2] | ||
| Name=DE_SIG | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/3] | ||
| Name=FMC1_IPMI | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/4] | ||
| Name=FMC2_IPMI | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/5] | ||
| Name=POWER | ||
| Clearance=0.1 | ||
| TrackWidth=0.381 | ||
| ViaDiameter=0.35 | ||
| ViaDrill=0.152 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/6] | ||
| Name=RTM_IO[14..0] | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/7] | ||
| Name=SE50 | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/8] | ||
| Name=SE60DE100 | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 | ||
| [pcbnew/Netclasses/9] | ||
| Name=SE_SIG | ||
| Clearance=0.127 | ||
| TrackWidth=0.254 | ||
| ViaDiameter=0.889 | ||
| ViaDrill=0.635 | ||
| uViaDiameter=0.508 | ||
| uViaDrill=0.127 | ||
| dPairWidth=0.2 | ||
| dPairGap=0.25 | ||
| dPairViaGap=0.25 |
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