- 👋 Hi, I’m @BrianHGinc
- 👀 I’m interested in FPGA System Verilog HDL source code and microcontroler coding.
- 🌱 I’m currently helping and offering free source code with embeded documentation.
- 💞️ I’m looking to help those integrate my source code into their projects.
- 📫 How to reach me here on github or at https://www.eevblog.com/forum/index.php as BrianHG in the FPGA section of the forum.
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BrianHG-DDR3-Controller
BrianHG-DDR3-Controller PublicDDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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Verilog-Floating-Point-Clock-Divider
Verilog-Floating-Point-Clock-Divider PublicProvide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
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SystemVerilog-HDMI-encoder-serializer-PLL-generator
SystemVerilog-HDMI-encoder-serializer-PLL-generator PublicSystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.
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Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor
Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor PublicVerilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.
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BHG_I2C_init_RS232_debugger
BHG_I2C_init_RS232_debugger PublicA Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.
SystemVerilog 5
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SystemVerilog-TestBench-BPM-picture-generator
SystemVerilog-TestBench-BPM-picture-generator PublicThis example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of yo…
SystemVerilog 5
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