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Added 48 bit Routines #453
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Commits on Nov 7, 2023
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Added: slland: 348 cycles sllor: 348 cycles sllxor: 381 cycles sllnot: 158 cycles sllcmpu: 210 cycles sllcmpzero: 45 cycles sllshl: varies sllshru: varies sllshrs: varies sllmulu: 1592 cycles
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Fixed interrupt issue and optimized to 108 cycles
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No longer backs up alt registers. Disables interrupts during the routine.
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Commits on Nov 8, 2023
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Updated documentation and made a very minor optimization
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Comparison of de to 0 simplified to comparison of de to hl
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Interrupt enabling and disabling now handled conditionally
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Now uses ude:uhl for minor shifts instead of uiy:uhl. Now uses stack for large shifts
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Commits on Nov 9, 2023
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Condensed routines. Eliminated most of sllshru. Fixed a bug where shifting 0 would cause a shift of 256.
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Commits on Nov 14, 2023
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Commits on Nov 23, 2023
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Added slldvrmu for 48 bit unsigned division and modulo (~6000 cycles). This is called from the slldivu and sllremu which are in one file as they share cleanup behavior.
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Commits on Dec 16, 2023
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Renamed Files to Match New Clang
Updated file names and documentation to use i48 instead of sll
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Commits on Dec 19, 2023
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Changed i48cmpu to no longer use arguments from stack
i48cmpu has been changed to the old commented out version which doesn't use arguments off stack. Also minor optimization.
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Commits on Dec 30, 2023
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Removed multiple stack uses, now about 100 cycles
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Commits on Jan 6, 2024
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Corrected how i48dvrmu Outputs
Changed i48dvrmu to put remainder in uiy:ubc rather than on the stack. i48dvrmu now restores interrupts and fully cleans up rather than partially relying on i48divu and i48remu.
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Commits on Jan 7, 2024
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Added i48cmps for signed int48_t comparison. 105 cycles.
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Added routines for i48 bit manipulation intrensics
Added i48bitrev, i48bswap, i48ctlz, i48popcnt. Significant optimization on i48bitrev and i48bswap may be possible. i48bitrev just does ibitrev twice without restoring af until the end, but an entirely new approach may perform better. i48bswap could be improved by using sp directly to manipulate stack values rather than hl (as lbswap does), but I was warned against doing this on prior routines.
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Commits on Jan 8, 2024
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i48cmpzero now outputs correct sign flag
Switched the order of register comparison so that routine outputs a sign flag matching the sign of the number.
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Commits on Feb 18, 2024
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Added i48neg, i48divs, and i48rems
i48neg contains routines for getting the negative of both uhl:ude and uiy:ubc. Signed division and remainder are about 10-500 more cycles than unsigned.
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Commits on Jun 13, 2024
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Cycles per loop is now 52 instead of 143. Base cost is slightly higher however (80 --> 279 cycles).
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Commits on Jun 20, 2024
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Decreased size and increased speed of division related routines
Removed backing up alt registers from i48dvrmu because based on other examples, they don't seem to need to be backed up. Streamlined other routines by reducing the amount of jumps used.
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