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potentially fixed hazard-detection
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Christer committed Nov 12, 2012
1 parent 000c3ca commit 218b66e
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Showing 44 changed files with 1,602 additions and 1,385 deletions.
12 changes: 6 additions & 6 deletions oving1/hazard_detection.stx
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Release 12.4 - xst M.81d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to Z:/github/tdt4255/oving1/xst/projnav.tmp
--> Parameter TMPDIR set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs

--> Parameter xsthdpdir set to Z:/github/tdt4255/oving1/xst
--> Parameter xsthdpdir set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst


Total REAL time to Xst completion: 0.00 secs
Expand Down Expand Up @@ -39,17 +39,17 @@ TABLE OF CONTENTS
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "\github\tdt4255\oving1\hazard_detection.vhd" into library work
Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\hazard_detection.vhd" into library work
Parsing entity <hazard_detection>.
Parsing architecture <Behavioral> of entity <hazard_detection>.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.21 secs
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.17 secs

-->

Total memory usage is 187952 kilobytes
Total memory usage is 187896 kilobytes

Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
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185 changes: 93 additions & 92 deletions oving1/hazard_detection.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:22:51 11/12/2012
-- Design Name:
-- Module Name: hazard_detection - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hazard_detection is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ex_zero : in STD_LOGIC;
ex_branch : in STD_LOGIC;
ex_mem_read : in STD_LOGIC;
ex_register_rt : in STD_LOGIC_VECTOR (4 downto 0);
id_register_rs : in STD_LOGIC_VECTOR (4 downto 0);
id_register_rt : in STD_LOGIC_VECTOR (4 downto 0);
reset_ifid : out STD_LOGIC;
reset_idex : out STD_LOGIC;
pc_write : out STD_LOGIC;
ifid_write : out STD_LOGIC;
stall_to_mux : out STD_LOGIC);
end hazard_detection;

architecture Behavioral of hazard_detection is

signal counter: integer := 0;

begin
process(CLK, RESET, ex_mem_read, ex_register_rt, ex_zero, ex_branch, id_register_rs, id_register_rt)
begin
if (RESET = '1') then
counter <= 0;
stall_to_mux <= '0';
reset_ifid <= '0';
reset_idex <= '0';
ifid_write <= '1';
pc_write <= '1';
elsif (counter = 0) then
if ((ex_mem_read = '1') and ((ex_register_rt = id_register_rs) or (ex_register_rt = id_register_rt))) then
-- stall for register read
counter <= 2;
reset_idex <= '0';
stall_to_mux <= '1';
pc_write <= '0';
ifid_write <= '0';
elsif((ex_zero = '1') and (ex_branch = '1')) then
-- flush for branching
reset_idex <= '1';
reset_ifid <= '1';
counter <= 1;
ifid_write <= '0';
else
-- no stalling
stall_to_mux <= '0';
reset_idex <= '0';
pc_write <= '1';
ifid_write <= '1';
end if;
else
if rising_edge(CLK) then
counter <= (counter - 1);
end if;
end if;
end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:22:51 11/12/2012
-- Design Name:
-- Module Name: hazard_detection - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hazard_detection is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ex_zero : in STD_LOGIC;
ex_branch : in STD_LOGIC;
ex_mem_read : in STD_LOGIC;
ex_register_rt : in STD_LOGIC_VECTOR (4 downto 0);
id_register_rs : in STD_LOGIC_VECTOR (4 downto 0);
id_register_rt : in STD_LOGIC_VECTOR (4 downto 0);
reset_ifid : out STD_LOGIC;
reset_idex : out STD_LOGIC;
pc_write : out STD_LOGIC;
ifid_write : out STD_LOGIC;
stall_to_mux : out STD_LOGIC);
end hazard_detection;

architecture Behavioral of hazard_detection is

signal counter: integer := 0;

begin
process(CLK, RESET, ex_mem_read, ex_register_rt, ex_zero, ex_branch, id_register_rs, id_register_rt)
begin
if (RESET = '1') then
counter <= 0;
stall_to_mux <= '0';
reset_ifid <= '0';
reset_idex <= '0';
ifid_write <= '1';
pc_write <= '1';
elsif (counter <= 0) and rising_edge(CLK) then
if ((ex_mem_read = '1') and ((ex_register_rt = id_register_rs) or (ex_register_rt = id_register_rt))) then
-- stall for register read
counter <= 2;
reset_idex <= '0';
stall_to_mux <= '1';
pc_write <= '0';
ifid_write <= '0';
elsif((ex_zero = '1') and (ex_branch = '1')) then
-- flush for branching
reset_idex <= '1';
reset_ifid <= '1';
counter <= 1;
ifid_write <= '0';
else
-- no stalling
stall_to_mux <= '0';
reset_ifid <= '0';
reset_idex <= '0';
pc_write <= '1';
ifid_write <= '1';
end if;
else
if rising_edge(CLK) then
counter <= (counter - 1);
end if;
end if;
end process;

end Behavioral;

102 changes: 51 additions & 51 deletions oving1/hazard_detection.xst
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set -tmpdir "Z:/github/tdt4255/oving1/xst/projnav.tmp"
set -xsthdpdir "Z:/github/tdt4255/oving1/xst"
run -compileonly yes
-p xc6slx16-2-csg324
-top hazard_detection
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
-ifn hazard_detection.prj
-ifmt mixed
set -tmpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp"
set -xsthdpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst"
run -compileonly yes
-p xc6slx16-2-csg324
-top hazard_detection
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
-ifn hazard_detection.prj
-ifmt mixed
2 changes: 1 addition & 1 deletion oving1/iseconfig/toplevel.xreport
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-11-12T21:42:43</DateModified>
<DateModified>2012-11-12T21:44:20</DateModified>
<ModuleName>toplevel</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/iseconfig/toplevel.xreport</SavedFilePath>
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