Implement ms timer and fix all timers

This will fix everything that uses a timer (or sleep).

Without this any function like eMMC/SD read/write/verify, TSEC/SE, etc can break when the time reaches the max value of the u32 microsecond timer (71minutes).

This fixes every possible breakage, including backup and restore (read/write/verify errors) that takes a lot of time.

The new max before a timer reset is now 48 days (the old one was 71 minutes)

ipl/btn.c

@@ -60,14 +60,14 @@ u32 btn_wait()
 
 u32 btn_wait_timeout(u32 time_ms, u32 mask)
 {
-	u32 timeout = get_tmr_us() + (time_ms * 1000);
+	u32 timeout = get_tmr_ms() + time_ms;
 	u32 res = btn_read() & mask;
 
 	do
 	{
 		if (!(res & mask))
 			res = btn_read() & mask;
-	} while (get_tmr_us() < timeout);
+	} while (get_tmr_ms() < timeout);
 
 	return res;
 }

ipl/clock.c

@@ -147,9 +147,9 @@ void clock_enable_kfuse()
 	CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100;
 	CLOCK(0x14) &= 0xFFFFFEFF;
 	CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100;
-	sleep(10);
+	usleep(10);
 	CLOCK(0x8) &= 0xFFFFFEFF;
-	sleep(20);
+	usleep(20);
 }
 
 void clock_disable_kfuse()
@@ -436,7 +436,7 @@ void clock_sdmmc_enable(u32 id, u32 val)
 	_clock_sdmmc_config_clock_source_inner(&div, id, val);
 	_clock_sdmmc_set_enable(id);
 	_clock_sdmmc_is_reset(id);
-	sleep((100000 + div - 1) / div);
+	usleep((100000 + div - 1) / div);
 	_clock_sdmmc_clear_reset(id);
 	_clock_sdmmc_is_reset(id);
 }

ipl/cluster.c

@@ -44,7 +44,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
 	u32 i = 5001;
 	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
 	{
-		sleep(1);
+		usleep(1);
 		i--;
 		if (i < 1)
 			return 0;
@@ -57,7 +57,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
 	{
 		if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
 			break;
-		sleep(1);
+		usleep(1);
 		i--;
 	}
 
@@ -74,7 +74,7 @@ void cluster_boot_cpu0(u32 entry)
 	if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
 	{
 		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
-		sleep(2);
+		usleep(2);
 		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
 		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
 		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;

ipl/di.c

@@ -33,10 +33,10 @@ static u32 _display_ver = 0;
 
 static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
 {
-	u32 end = TMR(0x10) + timeout;
-	while (TMR(0x10) < end && DSI(off) & mask)
+	u32 end = get_tmr_us() + timeout;
+	while (get_tmr_us() < end && DSI(off) & mask)
 		;
-	sleep(5);
+	usleep(5);
 }
 
 void display_init()
@@ -70,11 +70,11 @@ void display_init()
 	gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); //Backlight +-5V.
 	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); //Backlight +5V enable.
 
-	sleep(10000);
+	usleep(10000);
 
 	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); //Backlight -5V enable.
 
-	sleep(10000);
+	usleep(10000);
 
 	gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); //Backlight PWM, Enable, Reset.
 	gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
@@ -87,11 +87,11 @@ void display_init()
 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
 	exec_cfg((u32 *)DSI_BASE, _display_config_3, 60);
 
-	sleep(10000);
+	usleep(10000);
 
 	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH); //Backlight Reset enable.
 
-	sleep(60000);
+	usleep(60000);
 
 	DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
 	DSI(_DSIREG(DSI_WR_DATA)) = 0x337;
@@ -105,7 +105,7 @@ void display_init()
 	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
 	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
 
-	sleep(5000);
+	usleep(5000);
 
 	_display_ver = DSI(_DSIREG(DSI_RD_DATA));
 	if (_display_ver == 0x10)
@@ -114,25 +114,25 @@ void display_init()
 	DSI(_DSIREG(DSI_WR_DATA)) = 0x1105;
 	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
-	sleep(180000);
+	usleep(180000);
 
 	DSI(_DSIREG(DSI_WR_DATA)) = 0x2905;
 	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
-	sleep(20000);
+	usleep(20000);
 
 	exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
 	exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
 	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
 	exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);
 
-	sleep(10000);
+	usleep(10000);
 
 	exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
 	exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
 	exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);
 
-	sleep(10000);
+	usleep(10000);
 
 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
 }
@@ -161,27 +161,27 @@ void display_end()
 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
 	exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
 
-	sleep(10000);
+	usleep(10000);
 
 	if (_display_ver == 0x10)
 		exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
 
 	DSI(_DSIREG(DSI_WR_DATA)) = 0x1005;
 	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
-	sleep(50000);
+	usleep(50000);
 
 	//gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
 
-	//sleep(10000);
+	//usleep(10000);
 
 	//gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
 
-	//sleep(10000);
+	//usleep(10000);
 
 	//gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
 
-	//sleep(10000);
+	//usleep(10000);
 
 	//Disable clocks.
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;
@@ -209,7 +209,7 @@ void display_color_screen(u32 color)
 	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
 	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
 
-	sleep(35000);
+	usleep(35000);
 
 	display_backlight(1);
 }
@@ -221,7 +221,7 @@ u32 *display_init_framebuffer()
 	//This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768).
 	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);
 
-	sleep(35000);
+	usleep(35000);
 
 	//Enable backlight
 	//display_backlight(1);

ipl/hos.c

@@ -597,7 +597,7 @@ int hos_launch(ini_sec_t *cfg)
 	//Wait for secmon to get ready.
 	cluster_boot_cpu0(ctxt.pkg1_id->secmon_base);
 	while (!*mb_out)
-		sleep(1);
+		usleep(1);
 
 	//TODO: pkg1.1 locks PMC scratches, we can do that too at some point.
 	/*PMC(0x4) = 0x7FFFF3;

ipl/i2c.c

@@ -26,7 +26,7 @@ static void _i2c_wait(vu32 *base)
 	base[0x23] = 0x25;
 	for (u32 i = 0; i < 20; i++)
 	{
-		sleep(1);
+		usleep(1);
 		if (!(base[0x23] & 1))
 			break;
 	}
@@ -89,7 +89,7 @@ void i2c_init(u32 idx)
 
 	for (u32 i = 0; i < 10; i++)
 	{
-		sleep(20000);
+		usleep(20000);
 		if (base[0x1A] & 0x800)
 			break;
 	}

ipl/main.c

@@ -233,7 +233,7 @@ void mbist_workaround()
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
-	sleep(2);
+	usleep(2);
 
 	I2S(0x0A0) |= 0x400;
 	I2S(0x088) &= 0xFFFFFFFE;
@@ -247,7 +247,7 @@ void mbist_workaround()
 	I2S(0x488) &= 0xFFFFFFFE;
 	DISPLAY_A(0xCF8) |= 4;
 	VIC(0x8C) = 0xFFFFFFFF;
-	sleep(2);
+	usleep(2);
 
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
@@ -691,7 +691,7 @@ void reboot_rcm()
 	PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm.
 	PMC(0) |= 0x10;
 	while (1)
-		sleep(1);
+		usleep(1);
 }
 
 void power_off()
@@ -1028,7 +1028,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 			EPRINTFARGS("Error reading %d blocks @ LBA %08X,\nfrom eMMC (try %d), retrying...",
 				num, lba_curr, ++retryCount);
 
-			sleep(150000);
+			msleep(150);
 			if (retryCount >= 3)
 			{
 				gfx_con.fntsz = 16;
@@ -1305,7 +1305,7 @@ int restore_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part
 			EPRINTFARGS("Error writing %d blocks @ LBA %08X\nto eMMC (try %d), retrying...",
 				num, lba_curr, ++retryCount);
 
-			sleep(150000);
+			msleep(150);
 			if (retryCount >= 3)
 			{
 				gfx_con.fntsz = 16;
@@ -1376,7 +1376,7 @@ static void restore_emmc_selected(emmcPartType_t restoreType)
 	{
 		gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
 		gfx_printf(&gfx_con, "%kWait... (%ds)    %k", 0xFF888888, value, 0xFFCCCCCC);
-		sleep(1000000);
+		msleep(1000);
 		value--;
 	}
 	gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
@@ -1645,7 +1645,7 @@ void launch_firmware()
 	if (!cfg_sec)
 	{
 		gfx_printf(&gfx_con, "\nUsing default launch configuration...\n");
-		sleep(3000000);
+		msleep(3000);
 	}
 #ifdef MENU_LOGO_ENABLE
 	free(Kc_MENU_LOGO);
@@ -2118,7 +2118,7 @@ void print_battery_info()
 	for (int i = 0; i < 0x200; i += 2)
 	{
 		i2c_recv_buf_small(buf + i, 2, I2C_1, 0x36, i >> 1);
-		sleep(2500);
+		usleep(2500);
 	}
 
 	gfx_hexdump(&gfx_con, 0, (u8 *)buf, 0x200);
@@ -2174,18 +2174,18 @@ void print_battery_info()
 			if (btn & BTN_POWER)
 			{
 				max17050_fix_configuration();
-				sleep(1000000);
+				msleep(1000);
 				gfx_con_getpos(&gfx_con, &gfx_con.savedx,  &gfx_con.savedy);
 				u16 value = 0;
 				gfx_printf(&gfx_con, "%kThe console will power off in 45 seconds.\n%k", 0xFFFFDD00, 0xFFCCCCCC);
 				while (value < 46)
 				{
 					gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
 					gfx_printf(&gfx_con, "%2ds elapsed", value);
-					sleep(1000000);
+					msleep(1000);
 					value++;
 				}
-				sleep(2000000);
+				msleep(2000);
 
 				power_off();
 			}
@@ -2195,7 +2195,7 @@ void print_battery_info()
 	else
 		EPRINTF("You need a fully charged battery\nand connected to a wall adapter,\nto apply this fix!");
 
-	sleep(500000);
+	msleep(500);
 	btn_wait();
 } */
 
@@ -2224,7 +2224,7 @@ void print_battery_info()
 		{
 			gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
 			gfx_printf(&gfx_con, "%kWait... (%ds)   %k", 0xFF888888, value, 0xFFCCCCCC);
-			sleep(1000000);
+			msleep(1000);
 			value--;
 		}
 		gfx_con_setpos(&gfx_con, gfx_con.savedx, gfx_con.savedy);
@@ -2242,7 +2242,7 @@ void print_battery_info()
 				"2. Press POWER for 15s.\n"
 				"3. Reconnect the USB to power-on!%k\n", 0xFFFFDD00, 0xFFCCCCCC);
 		}
-		sleep(500000);
+		msleep(500);
 		btn_wait();
 	}
 }*/

ipl/max17050.c

@@ -236,7 +236,7 @@ int max17050_fix_configuration()
 	/* After Power up, the MAX17050 requires 500ms in order
 	 * to perform signal debouncing and initial SOC reporting
 	 */
-	sleep(500000);
+	msleep(500);
 
 	/* Initialize configaration */
 	_max17050_write_config_regs();
@@ -248,7 +248,7 @@ int max17050_fix_configuration()
 	/* delay must be atleast 350mS to allow VFSOC
 	 * to be calculated from the new configuration
 	 */
-	sleep(350000);
+	msleep(350);
 
 	/* reset vfsoc0 reg */
 	_max17050_reset_vfsoc0_reg();

ipl/max7762x.c

@@ -103,7 +103,7 @@ int max77620_regulator_set_voltage(u32 id, u32 mv)
 	u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr);
 	val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
 	i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val);
-	sleep(1000);
+	usleep(1000);
 
 	return 1;
 }
@@ -122,7 +122,7 @@ int max77620_regulator_enable(u32 id, int enable)
 	else
 		val &= ~reg->enable_mask;
 	i2c_send_byte(I2C_5, 0x3C, addr, val);
-	sleep(1000);
+	usleep(1000);
 
 	return 1;
 }

ipl/mc.c

@@ -127,7 +127,7 @@ void mc_enable()
 	//Enable EMC DLL clock.
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset.
-	sleep(5);
+	usleep(5);
 
 	//#ifdef CONFIG_ENABLE_AHB_REDIRECT
 	mc_disable_ahb_redirect();