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CakeML · Feb 18, 2019 · 1c2a4f4 · 1c2a4f4
1 parent f7ecfcc
commit 1c2a4f4
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/translator/Holmakefile b/translator/Holmakefile
@@ -1,2 +1,2 @@
 INCLUDES = .. \
-           ../example
+           ../ag32
diff --git a/translator/verilogTranslatorConfigLib.sml b/translator/verilogTranslatorConfigLib.sml
@@ -7,15 +7,15 @@ open verilogTranslatorCoreLib;
 
 (** Config **)
 
-(*
 open ag32MachineTheory;
 val state_ty = ``:state_circuit``;
 val fext_ty = ``:ext``;
-*)
 
+(*
 open circuitExampleTheory;
 val state_ty = ``:state``;
 val fext_ty = ``:ext_state``;
+*)
 
 (*
 open regexpExampleTheory;