risc2500/tasc: mistake in cycle compare

src/mame/drivers/saitek_risc2500.cpp

@@ -329,7 +329,7 @@ u32 risc2500_state::rom_r(offs_t offset)
 		u32 prev_pc = m_prev_pc;
 		m_prev_pc = pc;
 
-		if (diff >= 0)
+		if (diff > 0)
 		{
 			static constexpr int arm_branch_cycles = 3;
 			static constexpr int arm_max_cycles = 17; // datablock transfer

src/mame/drivers/tasc.cpp

@@ -11,8 +11,8 @@ on PC, however the prototype Gideon 2.1(internally: Rebel 2.01) is not.
 WARNING: Don't configure more than 512KB RAM for R30 The King 2.50, it will still
 be playable but will actually use less than 512KB RAM and become weaker.
 
-The King 2.23 version was not released to the public. It has an opening book
-meant for chesscomputer competitions.
+The King 2.23 version was not sold to consumers. It has an opening book meant
+for chesscomputer competitions.
 For more information, see: http://chesseval.com/ChessEvalJournal/R30v223.htm
 
 R30 hardware notes:
@@ -27,6 +27,9 @@ R40 hardware notes:
 - +512KB extra RAM piggybacked
 - rest same as R30
 
+Documentation for the Toshiba chips is hard to find, but similar chips exist:
+T7778 is equivalent to T6A39, T7900 is equivalent to T6A40.
+
 EPROMs are interchangable between R30 and R40, with some limitations with
 The King 2.50 (see below).
 
@@ -35,9 +38,6 @@ The King 2.50 appears to be protected against RAM upgrades though, and will
 limit itself to 128KB if it detects a non-default amount of RAM. Gideon doesn't
 use RAM above 128KB either, perhaps the R30 prototype only had 128KB RAM.
 
-Documentation for the Toshiba chips is hard to find, but similar chips exist:
-T7778 is equivalent to T6A39, T7900 is equivalent to T6A40.
-
 references:
 - https://www.schach-computer.info/wiki/index.php?title=Tasc_R30
 - https://www.schach-computer.info/wiki/index.php?title=Tasc_R40
@@ -235,7 +235,7 @@ u32 tasc_state::rom_r(offs_t offset)
 		u32 prev_pc = m_prev_pc;
 		m_prev_pc = pc;
 
-		if (diff >= 0)
+		if (diff > 0)
 		{
 			static constexpr int arm_branch_cycles = 3;
 			static constexpr int arm_max_cycles = 17; // datablock transfer