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Rollup merge of rust-lang#62281 - Disasm:riscv-pic, r=nagisa
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Add support for pc-relative addressing on 64-bit RISC-V

These changes allow Rust to generate position-independent code on `riscv64` targets with code model `medium`.

Closes: rust-lang#59802
See also: rust-embedded/riscv-rt#25, rust-embedded/wg#218
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@Centril
Centril committed Jul 6, 2019
2 parents fe3855c + c65ffa7 commit 5c6b58e
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Showing 3 changed files with 3 additions and 1 deletion.
1 change: 1 addition & 0 deletions src/librustc_target/spec/riscv64gc_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ pub fn target() -> TargetResult {
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
code_model: Some("medium".to_string()),
emit_debug_gdb_scripts: false,
abi_blacklist: super::riscv_base::abi_blacklist(),
eliminate_frame_pointer: false,
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1 change: 1 addition & 0 deletions src/librustc_target/spec/riscv64imac_unknown_none_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ pub fn target() -> TargetResult {
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
code_model: Some("medium".to_string()),
emit_debug_gdb_scripts: false,
abi_blacklist: super::riscv_base::abi_blacklist(),
eliminate_frame_pointer: false,
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2 changes: 1 addition & 1 deletion src/llvm-project
Submodule llvm-project updated 23 files
+11 −0 llvm/include/llvm/CodeGen/MachineBasicBlock.h
+4 −1 llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+77 −21 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+7 −0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+1 −0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+2 −0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+3 −0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
+3 −0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+6 −1 llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+4 −3 llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
+80 −0 llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+67 −41 llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+4 −0 llvm/lib/Target/RISCV/RISCVISelLowering.h
+2 −0 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+5 −1 llvm/lib/Target/RISCV/RISCVInstrInfo.td
+9 −0 llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+2 −0 llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+80 −0 llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+85 −0 llvm/test/CodeGen/RISCV/pic-models.ll
+34 −0 llvm/test/MC/RISCV/relocations.s
+6 −6 llvm/test/MC/RISCV/rv32i-invalid.s
+22 −0 llvm/test/MC/RISCV/rvi-pseudos-invalid.s
+47 −2 llvm/test/MC/RISCV/rvi-pseudos.s

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