The objective of this design project is to create a simple project using any/all knowledge of VHDL learned in class. The project chosen will be a 4-bit finite state machine (FSM) composed of 16 states (0 to 15). Each state will be shown on a computer monitor over VGA as well as on LEDs. Each state has a unique output that will be displayed on 4 8-segment displays that will be transitioned to after every second if an enable switch is on. A display switch is used to switch between the unique output or the current time and state number. This should be tested on an FPGA board (ex. Altera DE1 board) after appropriate pin assignments.
Intel Quartus Prime was used. View VLSI VGA Interface Design Project.docx for more details.
Project reference: https://www.youtube.com/watch?v=WK5FT5RD1sU&list=PL1DkxbR7EEdS1LCYjthk1dnizQoKfzZPV&index=1