fix OUT FIFO shift and pop logic

DangerousPrototypes · May 26, 2019 · 3ad6f1e · 3ad6f1e
1 parent 7a42f88
commit 3ad6f1e
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Showing 2 changed files with 26 additions and 20 deletions.
diff --git a/hdl/buspirate/buspirate.v b/hdl/buspirate/buspirate.v
@@ -41,7 +41,8 @@ module top (clock, reset,
     wire buftdi_mosi,buftdi_clock,buftdi_miso,buftdi_cs,buftdi_aux;
     // Memory controller interface
     wire [MC_DATA_WIDTH-1:0] mc_din;
-    reg [MC_DATA_WIDTH-1:0] mc_dout;
+    wire [MC_DATA_WIDTH-1:0] mc_dout;
+    reg [MC_DATA_WIDTH-1:0] mc_dout_reg;
 
 
 
@@ -59,6 +60,7 @@ module top (clock, reset,
     // sync signals
     wire spi_go;					// starts a SPI transmission
     wire spi_state;				// state of module (0=idle, 1=busy/transmitting)
+    reg spi_state_last;
     // data in/out
     wire [7:0] spi_din; 			// data in (will get transmitted)
     wire [7:0] spi_dout;				// data out (will get received)
@@ -91,7 +93,9 @@ module top (clock, reset,
 
       //FIFO
       wire in_fifo_in_nempty, in_fifo_in_full, in_fifo_out_nempty,in_fifo_in_shift,in_fifo_out_pop;
-      wire out_fifo_in_nempty, out_fifo_in_full, out_fifo_out_nempty,out_fifo_out_data;
+      wire out_fifo_in_nempty, out_fifo_in_full, out_fifo_out_nempty;
+      wire [MC_DATA_WIDTH-1:0] out_fifo_out_data;
+      reg out_fifo_in_shift;
 
       fifo FIFO_IN (
       	.clock(clock),
@@ -129,14 +133,17 @@ module top (clock, reset,
     assign in_fifo_in_shift=(mc_add===6'h00)?mc_we_sync:1'b0; //follow the we signal
     assign in_fifo_out_pop=!spi_state;
     assign spi_go=(in_fifo_out_nempty && !spi_state)? 1'b1:1'b0; //if pending FIFO and SPI idle
-    assign out_fifo_in_shift=!spi_state; //?? how to trigger the move of spi read to FIFO???
+    //assign out_fifo_in_shift=!spi_state; //?? how to trigger the move of spi read to FIFO???
+    assign mc_dout=(mc_add===6'h00&&!mc_oe)?out_fifo_out_data:mc_dout_reg;
     assign out_fifo_out_pop=(mc_add===6'h00)?mc_oe_sync:1'b0;//follow the oe signal
 
     assign pwm_reset=(mc_add===6'h1a)?!mc_we_sync:1'b0; //reset pwm counters after write to pwm
 
     //writes
     always @(posedge clock)
     begin
+      spi_state_last<=spi_state;
+      out_fifo_in_shift<=((spi_state_last===1'b1)&&(spi_state===1'b0));
       if(mc_we_sync) begin
       case(mc_add)
         6'h19:									// pwm on-time register
@@ -150,17 +157,13 @@ module top (clock, reset,
       endcase
       end else if (mc_oe_sync) begin
       case(mc_add)
-        6'h00:
-          begin
-            mc_dout<=out_fifo_out_data;
-          end
         6'h19:									// pwm on-time register
           begin
-            mc_dout<= pwm_on;
+            mc_dout_reg<= pwm_on;
           end
         6'h1a:									// pwm off-time register
           begin
-            mc_dout<=pwm_off;
+            mc_dout_reg<=pwm_off;
           end
       endcase
       end

diff --git a/hdl/buspirate/buspirate_tb.gtkw b/hdl/buspirate/buspirate_tb.gtkw
@@ -1,21 +1,21 @@
 [*]
 [*] GTKWave Analyzer v3.3.77 (w)1999-2016 BSI
-[*] Sun May 26 13:17:42 2019
+[*] Sun May 26 13:50:13 2019
 [*]
 [dumpfile] "C:\Users\ian\Desktop\buspirateultra\hdl\buspirate\buspirate_tb.vcd"
-[dumpfile_mtime] "Sun May 26 13:02:30 2019"
-[dumpfile_size] 44556
+[dumpfile_mtime] "Sun May 26 13:46:44 2019"
+[dumpfile_size] 44680
 [savefile] "C:\Users\ian\Desktop\buspirateultra\hdl\buspirate\buspirate_tb.gtkw"
-[timestart] 1340000
-[size] 1920 1017
+[timestart] 1600000
+[size] 1284 649
 [pos] -1 -1
-*-18.427427 1659000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-19.427427 2502000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] buspirate_tb.
 [treeopen] buspirate_tb.buspirate.
-[sst_width] 331
+[sst_width] 211
 [signals_width] 218
 [sst_expanded] 1
-[sst_vpaned_height] 301
+[sst_vpaned_height] 272
 @28
 buspirate_tb.buspirate.clock
 buspirate_tb.buspirate.mc_we
@@ -38,15 +38,18 @@ buspirate_tb.buspirate.SPI_MASTER.data_o[7:0]
 @28
 buspirate_tb.buspirate.SPI_MASTER.go
 buspirate_tb.buspirate.SPI_MASTER.rst
-@29
 buspirate_tb.buspirate.SPI_MASTER.state
 @200
 -FIFO_OUT
 @28
 [color] 2
 buspirate_tb.buspirate.FIFO_OUT.in_shift
-[color] 2
-buspirate_tb.buspirate.FIFO_OUT.next_in_pos[1:0]
+buspirate_tb.buspirate.FIFO_OUT.in_pos[1:0]
+buspirate_tb.buspirate.FIFO_OUT.in_full
+@22
+buspirate_tb.buspirate.FIFO_OUT.in_data[7:0]
+@23
+buspirate_tb.buspirate.FIFO_OUT.out_data[7:0]
 @200
 -FIFO_IN
 @22