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Popular repositories

  1. iiitb_usr iiitb_usr Public

    This project analyses and simulates the operations of a 4-bit Universal Shift Register. The Register can take data and control inputs from the user and execute data operations according to the mode…

    Verilog

  2. caravel_iiitb_usr caravel_iiitb_usr Public

    Verilog

  3. OpenFASOC OpenFASOC Public

    Python

  4. OPENFASOC-1 OPENFASOC-1 Public

    Forked from Bandaanusha/OPENFASOC

  5. OpenFaSoc-2 OpenFaSoc-2 Public

    Forked from vinayrayapati/OpenFaSoc

    Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits

    Python