iiitb_usr - Universal Shift Register (USR)

This project analyses and simulates the operations of a 4-bit Universal Shift Register. The Register can take data and control inputs from the user and execute data operations according to the mode of operation specified.

About USR: Introduction

A Universal Shift Register is a register with both right shift and left shift with parallel load capabilities. Universal Shift Registers are used as memory elements in computers. A Unidirectional Shift Register shifts in only one direction whereas a Bidirectional Shift Register is capable of shifting in both the directions. The design of Universal Shift Register is a combination of Bidirectional Shift Register and a Unidirectional Shift Register with provision for parallel.

A 4-bit Universal Shift Register consists of 4 flip-flops and 4 4×1 multiplexers. All the 4 multiplexers share the same select lines (S1 and S0) which select the mode of operation for the shift register. The select line inputs choose the suitable input for the flip-flops.

Circuit Design

This model has the following connections:

1. The first input is connected to the output pin of the corresponding flip-flop.
2. The second input is connected to the output of the very-previous flip flop which initiates the right shift.
3. The third input is connected to the output of the very-next flip-flop which facilitates the left shift.
4. The fourth input is connected to the individual bits of the input data which helps in parallel loading.

The working of the Universal Shift Register depends on the inputs given to the select lines.

Modes of Operation:

According to the inputs to the select lines, the following modes can be implemented in a Universal Shift Register:

1. The input '00' to the select lines refers to "locked state" wherein the register contents remain unchanged.
2. The input '01' refers to "right shift" meaning that the register contents will be shifted towards the right.
3. The input '10' indicates "left shift" which shifts the contents of the register to the left.
4. The input '11' to the select line reflects parallel loading of data into the register.

Advantages of Universal Shift Register

1. Has the ability to perform 3 operations: shift-left, shift-right, and parallel loading.
2. Temporary storage of data within register.
3. Capable of performing serial to serial, serial to parallel, parallel to serial and parallel to parallel operations.
4. Acts as an interface between devices during data transfer.

Applications

1. Used in micro-controllers for I/O expansion
2. Used as a serial-to-serial, parallel-to-parallel, serial-to-parallel data converter respectively.
3. Used in parallel and serial to serial data transfer.
4. Used as a memory element in computers.
5. Used in time delay and data manipulation applications.
6. Used in frequency counters, binary counters and digital clocks.

Tools Used

iverilog and GTKWave Installation

• Icarus Verilog is an implementation for the IEEE-1364 Verilog hardware description language. It is a Verilog simulation and synthesis tool.
• GTKWave is a VCD waveform viewer based on the GTK library. This viewer supports VCD and LXT formats for signal dumps. GTKWave reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing.

For Ubuntu Open your terminal and type the following to install iverilog and GTKWave:

$   sudo apt-get update
$   sudo apt-get install iverilog gtkwave

Yosys Installation

• Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
• more at https://yosyshq.net/yosys/

To install yosys follow the instructions given in the following github repository:

• https://github.com/YosysHQ/yosys/blob/master/README.md#installation

Installation of OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

Follow the steps from the below git repository to install OpenLane on Ubuntu:

https://github.com/The-OpenROAD-Project/OpenLane>https://github.com/The-OpenROAD-Project/OpenLane

Installation of Magic

Enter the following commands to install the prerequisite files prior to Magic setup:

$ sudo apt-get update 
$ sudo apt-get install csh
$ sudo apt-get install x11
$ sudo apt-get install xorg
$ sudo apt-get install xorg openbox
$ sudo apt-get install freeglut3-dev
$ sudo apt-get install tcl-dev tk-dev

Commands for setting up Magic:

$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic
$ ./configure
$ make
$ sudo make install

Simulation and Synthesis

Functional Simulation

To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal:

$   sudo apt install -y git
$   git clone https://github.com/DebanganaMukherjee/iiitb_usr.git
$   cd iiitb_usr
$   iverilog iiitb_usr.v iiitb_usr_tb.v
$   ./a.out
$   gtkwave dump.vcd

About Synthesis

Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.

Synthesis takes place in multiple steps:

• Converting RTL into simple logic gates.
• Mapping those gates to actual technology-dependent logic gates available in the technology libraries.
• Optimizing the mapped netlist keeping the constraints set by the designer intact

Invoke 'yosys' and execute the below commands to perform the synthesis of the above circuit:

$   read_liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$   read_verilog iiitb_usr.v 
$   synth -top usr
$   dfflibmap -liberty ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib  
$   abc -liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$   show
$   stat

Gate Level Simulation (GLS)

GLS implies running the testbench with netlist as the design under test. It is used to verify the logical correctness of the design after synthesis. It also ensures that the timing constraints are met. Execute below commands in the project directory to perform GLS:

$   iverilog ./verilog_model/primitives.v ./verilog_model/sky130_fd_sc_hd.v usr_netlist.v iiitb_usr_tb.v
$   ./a.out
$   gtkwave dump.vcd

Functional Characteristics

Pre Synthesis Simulation Results

The Simulation Results for input data = '1001' are as follows:

The above simulation displays Parallel Loading, Right Shift, Left Shift and Locked State (No Change) operations respectively on input data '1001'.

Netlist Representation

Post Synthesis Statistics

Can be displayed with yosys command 'stat':

Post Synthesis Simulation Results

Simulation (GLS) after Netlist generation:

Layout

After completion of Synthesis, we can proceed towards the steps of physical design. For this, we use OpenLane flow.

Prerequisites

To run a custom design on openlane, navigate to the Openlane folder and run the following commands:

$ cd designs

$ mkdir iiitb_usr

$ cd iiitb_usr

$ mkdir src

$ touch config.json

$ cd src

$ touch iiitb_usr.v

Kindly note that the iiitb_usr.v file should contain the verilog RTL code you have used to get your post synthesis simulation result.

Copy the following files to src folder in your design:

• sky130_fd_sc_hd__fast.lib
• sky130_fd_sc_hd__slow.lib
• sky130_fd_sc_hd__typical.lib
• sky130_vsdinv.lef files The src folder should finally contain:

The config.json folder present within the "iiitb_usr" folder should be modified as follows: Note: Add the verilog topmost module name under 'design_name'.

Next navigate to the Openlane folder in terminal and give the following command:

$ sudo make mount 

After entering the Openlane container give the following command:

$ ./flow.tcl -interactive

This command opens the interactive tcl console. In the tcl console type the following commands:

% package require openlane 0.9
% prep -design iiitb_usr

The following commands are to merge the external the lef files to the merged.nom.lef file.

% set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
% add_lefs -src $lefs

The contents of the merged.nom.lef file should contain the macro definition of "sky130_vsdinv":

Synthesis

% run_synthesis

Synthesis Reports

• Including vsdinv:

• Excluding vsdinv:

Highlighted D-flipflops used in design:

Setup and Hold Slack Post synthesis:

Flop Ratio:

Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 4/16 = 0.25

The sky130_vsdinv should also reflect in your netlist after synthesis:

Floorplan

% run_floorplan

Floorplan Reports

The die area and the core area report can be found in <current_run_dir>/reports/floorplan as 3-initial_fp_die_area.rpt and 3-initial_fp_core_area.rpt respectively.

• Die Area:

• Core Area:

View the floorplan, using the below magic command in the terminal opened in the directory: <current_run_directory>/results/floorplan

$ magic -T /home/debangana3/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read usr.def &

Floorplan view:

Refer below for the cells on floorplan (can be found by zooming into the left bottom corner):

Placement

% run_placement

Placement Reports

View the placement in the layout, using the below Magic command in the terminal opened in the directory: <current_run_directory>/results/placement

$ magic -T /home/debangana3/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read usr.def &

Placement View

Placement view showing the sky130_vsdinv cells:

The sky130_vsdinv should also reflect in your netlist after placement:

Clock Tree Synthesis

% run_cts

Routing

% run_routing

Routing Reports

View the layout after routing, using the below magic command in the terminal opened in the directory: <current_run_directory>/results/routing

$ magic -T /home/debangana3/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read usr.def &

Routing View

• Without including vsdinv:

Area Report Post-Routing: Area of design calculated to be: 2467.272 um2 (square micrometers)

Power Report: Total power consumed: 92.6 uW (microwatts)

• Using vsdinv:

Routing view showing sky130_vsdinv (Cell 23):

Area report using Magic :

The sky130_vsdinv should be visible in your netlist post-routing:

STA

Run the entire flow using a single command:

./flow.tcl -design iiitb_usr

Install OpenSTA using:

$ sudo apt install opensta

After entering your home directory, run the following:

OpenSTA/app/sta

This opens your STA base. Next type in the following:

% read_liberty -max /home/debangana3/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib
% read_liberty -min /home/debangana3/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib
% read_verilog /home/debangana3/OpenLane/designs/iiitb_usr_1/runs/RUN_2022.09.27_15.14.27/results/routing/usr.resized.v
% link_design usr
% read_sdc /home/debangana3/OpenLane/designs/iiitb_usr_1/runs/RUN_2022.09.27_15.14.27/results/cts/usr.sdc
% read_spef /home/debangana3/OpenLane/designs/iiitb_usr_1/runs/RUN_2022.09.27_15.14.27/results/routing/usr.nom.spef
% set_propagated_clock [all_clocks]
% report_checks

Maximum Positive Slack: 7.16 ns

Frequency = 1/ (Clock period-Slack) = 1/(10-7.16) = 352.1 MHz (time is in nanoseconds)

Contributors

• Debangana Mukherjee
• Kunal Ghosh

Acknowledgements

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.

Contact Information

• Debangana Mukherjee, Research Scholar at International Institute of Information Technology, Bangalore (debangana.mukherjee@iiitb.ac.in)
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. (kunalghosh@gmail.com)

References

• www.geeksforgeeks.org/universal-shift-register-in-digital-logic/
• https://media.cheggcdn.com/media/d06/phpjKEYI9
• For verilog code and testbench: https://youtu.be/kVMb3seJKhI