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Add SPC700 ISA definition
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@exodustx0
exodustx0 committed Nov 14, 2021
1 parent 0d4c430 commit d719de2
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12 changes: 11 additions & 1 deletion Common/Plugins/DasmDataInspectorPlugin.ini
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; A maximum of 8 Disassembly type names are currently supported.
; Each included type adds to HxD load time, as the definition files are parsed on DLL initialization.
; If HxD load time is an issue, only include the actual DasmTypes that you currently require. :)
DasmTypes=6502,65C02,W65C02S,65C816,6800,6809
DasmTypes=6502,65C02,W65C02S,65C816,6800,6809,SPC700

; NOTES:
; Each DasmType type name also defines the Disassembly name that will appear in the HxD DataInspector grid.
Expand Down Expand Up @@ -106,4 +106,14 @@ DefinitionFileName=Dasm6809.csv
DefinitionLogEnable=0
DefinitionLogPath=C:\Temp

[SPC700]
MaxInstructionByteCount=3
OperandEndianness=Little
FirstOperandWildcard=?
SecondOperandWildcard=^
DefinitionFilePath=Plugins
DefinitionFileName=DasmSPC700.csv
DefinitionLogEnable=0
DefinitionLogPath=C:\Temp


257 changes: 257 additions & 0 deletions Common/Plugins/DasmSPC700.csv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,257 @@
OpcodeBytes,OperandBytes,FirstOperandMask,FirstOperandHexDec,FirstOperandSignedUnsigned,SecondOperandMask,SecondOperandHexDec,SecondOperandSignedUnsigned,AssemblyString
00,,,,,,,,"NOP"
01,,,,,,,,"TCALL 0"
02,00,FF,H,U,,,,"SET1 ?.0"
03,0000,FF00,H,U,00FF,H,S,"BBS ?.0, ^"
04,00,FF,H,U,,,,"OR A, ?"
05,0000,FFFF,H,U,,,,"OR A, ?"
06,,,,,,,,"OR A, (X)"
07,00,FF,H,U,,,,"OR A, [?+X]"
08,00,FF,H,U,,,,"OR A, #?"
09,0000,FF00,H,U,00FF,H,U,"OR ^, ?"
0A,0000,FF1F,H,U,00E0,D,U,"OR1 C, ?.^"
0B,00,FF,H,U,,,,"ASL ?"
0C,0000,FFFF,H,U,,,,"ASL ?"
0D,,,,,,,,"PUSH PSW"
0E,0000,FFFF,H,U,,,,"TSET1 ?"
0F,,,,,,,,"BRK"
10,00,FF,H,S,,,,"BPL ?"
11,,,,,,,,"TCALL 1"
12,00,FF,H,U,,,,"CLR1 ?.0"
13,0000,FF00,H,U,00FF,H,S,"BBC ?.0, ^"
14,00,FF,H,U,,,,"OR A, ?+X"
15,0000,FFFF,H,U,,,,"OR A, ?+X"
16,0000,FFFF,H,U,,,,"OR A, ?+Y"
17,00,FF,H,U,,,,"OR A, [?]+Y"
18,0000,FF00,H,U,00FF,H,U,"OR ^, #?"
19,,,,,,,,"OR (X), (Y)"
1A,00,FF,H,U,,,,"DECW ?"
1B,00,FF,H,U,,,,"ASL ?+x"
1C,,,,,,,,"ASL A"
1D,,,,,,,,"DEC X"
1E,0000,FFFF,H,U,,,,"CMP X, ?"
1F,0000,FFFF,H,U,,,,"jmp [?+X]"
20,,,,,,,,"CLRP"
21,,,,,,,,"TCALL 2"
22,00,FF,H,U,,,,"SET1 ?.1"
23,0000,FF00,H,U,00FF,H,S,"BBS ?.1, ^"
24,00,FF,H,U,,,,"AND A, ?"
25,0000,FFFF,H,U,,,,"AND A, ?"
26,,,,,,,,"AND A, (X)"
27,00,FF,H,U,,,,"AND A, [?+X]"
28,00,FF,H,U,,,,"AND A, #?"
29,0000,FF00,H,U,00FF,H,U,"AND ^, ?"
2A,0000,FF1F,H,U,00E0,D,U,"OR1 C, /?.^"
2B,00,FF,H,U,,,,"ROL ?"
2C,0000,FFFF,H,U,,,,"ROL ?"
2D,,,,,,,,"PUSH A"
2E,0000,FF00,H,U,00FF,H,S,"CBNE ?, ^"
2F,00,FF,H,S,,,,"BRA ?"
30,00,FF,H,S,,,,"BMI ?"
31,,,,,,,,"TCALL 3"
32,00,FF,H,U,,,,"CLR1 ?.1"
33,0000,FF00,H,U,00FF,H,S,"BBC ?.1, ^"
34,00,FF,H,U,,,,"AND A, ?+X"
35,0000,FFFF,H,U,,,,"AND A, ?+X"
36,0000,FFFF,H,U,,,,"AND A, ?+Y"
37,00,FF,H,U,,,,"AND A, [?]+Y"
38,0000,FF00,H,U,00FF,H,U,"AND ^, #?"
39,,,,,,,,"AND (X), (Y)"
3A,00,FF,H,U,,,,"INCW ?"
3B,00,FF,H,U,,,,"ROL ?+x"
3C,,,,,,,,"ROL A"
3D,,,,,,,,"INC X"
3E,00,FF,H,U,,,,"CMP X, ?"
3F,0000,FFFF,H,U,,,,"CALL ?"
40,,,,,,,,"SETP"
41,,,,,,,,"TCALL 4"
42,00,FF,H,U,,,,"SET1 ?.2"
43,0000,FF00,H,U,00FF,H,S,"BBS ?.2, ^"
44,00,FF,H,U,,,,"EOR A, ?"
45,0000,FFFF,H,U,,,,"EOR A, ?"
46,,,,,,,,"EOR A, (X)"
47,00,FF,H,U,,,,"EOR A, [?+X]"
48,00,FF,H,U,,,,"EOR A, #?"
49,0000,FF00,H,U,00FF,H,U,"EOR ^, ?"
4A,0000,FF1F,H,U,00E0,D,U,"AND1 C, ?.^"
4B,00,FF,H,U,,,,"LSR ?"
4C,0000,FFFF,H,U,,,,"LSR ?"
4D,,,,,,,,"PUSH X"
4E,0000,FFFF,H,U,,,,"TCLR1 ?"
4F,00,FF,H,U,,,,"PCALL ?"
50,00,FF,H,S,,,,"BVC ?"
51,,,,,,,,"TCALL 5"
52,00,FF,H,U,,,,"CLR1 ?.2"
53,0000,FF00,H,U,00FF,H,S,"BBC ?.2, ^"
54,00,FF,H,U,,,,"EOR A, ?+X"
55,0000,FFFF,H,U,,,,"EOR A, ?+X"
56,0000,FFFF,H,U,,,,"EOR A, ?+Y"
57,00,FF,H,U,,,,"EOR A, [?]+Y"
58,0000,FF00,H,U,00FF,H,U,"EOR ^, #?"
59,,,,,,,,"EOR (X), (Y)"
5A,00,FF,H,U,,,,"CMPW YA, ?"
5B,00,FF,H,U,,,,"LSR ?+x"
5C,,,,,,,,"LSR A"
5D,,,,,,,,"MOV X, A"
5E,0000,FFFF,H,U,,,,"CMP Y, ?"
5F,0000,FFFF,H,U,,,,"JMP ?"
60,,,,,,,,"CLRC"
61,,,,,,,,"TCALL 6"
62,00,FF,H,U,,,,"SET1 ?.3"
63,0000,FF00,H,U,00FF,H,S,"BBS ?.3, ^"
64,00,FF,H,U,,,,"CMP A, ?"
65,0000,FFFF,H,U,,,,"CMP A, ?"
66,,,,,,,,"CMP A, (X)"
67,00,FF,H,U,,,,"CMP A, [?+X]"
68,00,FF,H,U,,,,"CMP A, #?"
69,0000,FF00,H,U,00FF,H,U,"CMP ^, ?"
6A,0000,FF1F,H,U,00E0,D,U,"AND1 C, /?.^"
6B,00,FF,H,U,,,,"ROR ?"
6C,0000,FFFF,H,U,,,,"ROR ?"
6D,,,,,,,,"PUSH Y"
6E,0000,FF00,H,U,00FF,H,S,"DBNZ ?, ^"
6F,,,,,,,,"RET"
70,00,FF,H,S,,,,"BVS ?"
71,,,,,,,,"TCALL 7"
72,00,FF,H,U,,,,"CLR1 ?.3"
73,0000,FF00,H,U,00FF,H,S,"BBC ?.3, ^"
74,00,FF,H,U,,,,"CMP A, ?+X"
75,0000,FFFF,H,U,,,,"CMP A, ?+X"
76,0000,FFFF,H,U,,,,"CMP A, ?+Y"
77,00,FF,H,U,,,,"CMP A, [?]+Y"
78,0000,FF00,H,U,00FF,H,U,"CMP ^, #?"
79,,,,,,,,"CMP (X), (Y)"
7A,00,FF,H,U,,,,"ADDW YA, ?"
7B,00,FF,H,U,,,,"ROR ?+x"
7C,,,,,,,,"ROR A"
7D,,,,,,,,"MOV A, X"
7E,00,FF,H,U,,,,"CMP Y, ?"
7F,,,,,,,,"RETI"
80,,,,,,,,"SETC"
81,,,,,,,,"TCALL 8"
82,00,FF,H,U,,,,"SET1 ?.4"
83,0000,FF00,H,U,00FF,H,S,"BBS ?.4, ^"
84,00,FF,H,U,,,,"ADC A, ?"
85,0000,FFFF,H,U,,,,"ADC A, ?"
86,,,,,,,,"ADC A, (X)"
87,00,FF,H,U,,,,"ADC A, [?+X]"
88,00,FF,H,U,,,,"ADC A, #?"
89,0000,FF00,H,U,00FF,H,U,"ADC ^, ?"
8A,0000,FF1F,H,U,00E0,D,U,"EOR1 C, ?.^"
8B,00,FF,H,U,,,,"DEC ?"
8C,0000,FFFF,H,U,,,,"DEC ?"
8D,00,FF,H,U,,,,"MOV Y, #?"
8E,,,,,,,,"POP PSW"
8F,0000,FF00,H,U,00FF,H,U,"MOV ^, #?"
90,00,FF,H,S,,,,"BCC ?"
91,,,,,,,,"TCALL 9"
92,00,FF,H,U,,,,"CLR1 ?.4"
93,0000,FF00,H,U,00FF,H,S,"BBC ?.4, ^"
94,00,FF,H,U,,,,"ADC A, ?+X"
95,0000,FFFF,H,U,,,,"ADC A, ?+X"
96,0000,FFFF,H,U,,,,"ADC A, ?+Y"
97,00,FF,H,U,,,,"ADC A, [?]+Y"
98,0000,FF00,H,U,00FF,H,U,"ADC ^, #?"
99,,,,,,,,"ADC (X), (Y)"
9A,00,FF,H,U,,,,"SUBW YA, ?"
9B,00,FF,H,U,,,,"DEC ?+x"
9C,,,,,,,,"DEC A"
9D,,,,,,,,"MOV X, SP"
9E,,,,,,,,"DIV YA, X"
9F,,,,,,,,"XCN A"
A0,,,,,,,,"EI"
A1,,,,,,,,"TCALL 10"
A2,00,FF,H,U,,,,"SET1 ?.5"
A3,0000,FF00,H,U,00FF,H,S,"BBS ?.5, ^"
A4,00,FF,H,U,,,,"SBC A, ?"
A5,0000,FFFF,H,U,,,,"SBC A, ?"
A6,,,,,,,,"SBC A, (X)"
A7,00,FF,H,U,,,,"SBC A, [?+X]"
A8,00,FF,H,U,,,,"SBC A, #?"
A9,0000,FF00,H,U,00FF,H,U,"SBC ^, ?"
AA,0000,FF1F,H,U,00E0,D,U,"MOV1 C, ?.^"
AB,00,FF,H,U,,,,"INC ?"
AC,0000,FFFF,H,U,,,,"INC ?"
AD,00,FF,H,U,,,,"CMP Y, #?"
AE,,,,,,,,"POP A"
AF,,,,,,,,"MOV (X)+, A"
B0,00,FF,H,S,,,,"BCS ?"
B1,,,,,,,,"TCALL 11"
B2,00,FF,H,U,,,,"CLR1 ?.5"
B3,0000,FF00,H,U,00FF,H,S,"BBC ?.5, ^"
B4,00,FF,H,U,,,,"SBC A, ?+X"
B5,0000,FFFF,H,U,,,,"SBC A, ?+X"
B6,0000,FFFF,H,U,,,,"SBC A, ?+Y"
B7,00,FF,H,U,,,,"SBC A, [?]+Y"
B8,0000,FF00,H,U,00FF,H,U,"SBC ^, #?"
B9,,,,,,,,"SBC (X), (Y)"
BA,00,FF,H,U,,,,"MOVW YA, ?"
BB,00,FF,H,U,,,,"INC ?+x"
BC,,,,,,,,"INC A"
BD,,,,,,,,"MOV SP, X"
BE,,,,,,,,"DAS A"
BF,,,,,,,,"MOV A, (X)+"
C0,,,,,,,,"DI"
C1,,,,,,,,"TCALL 12"
C2,00,FF,H,U,,,,"SET1 ?.6"
C3,0000,FF00,H,U,00FF,H,S,"BBS ?.6, ^"
C4,00,FF,H,U,,,,"MOV ?, A"
C5,0000,FFFF,H,U,,,,"MOV ?, A"
C6,,,,,,,,"MOV (X), A"
C7,00,FF,H,U,,,,"MOV [?+X], A"
C8,00,FF,H,U,,,,"CMP X, #?"
C9,0000,FFFF,H,U,,,,"MOV ?, X"
CA,0000,FF1F,H,U,00E0,D,U,"MOV1 ?.^, C"
CB,00,FF,H,U,,,,"MOV ?, Y"
CC,0000,FFFF,H,U,,,,"MOV ?, Y"
CD,00,FF,H,U,,,,"MOV X, #?"
CE,,,,,,,,"POP X"
CF,,,,,,,,"MUL YA"
D0,00,FF,H,S,,,,"BNE ?"
D1,,,,,,,,"TCALL 13"
D2,00,FF,H,U,,,,"CLR1 ?.6"
D3,0000,FF00,H,U,00FF,H,S,"BBC ?.6, ^"
D4,00,FF,H,U,,,,"MOV ?+X, A"
D5,0000,FFFF,H,U,,,,"MOV ?+X, A"
D6,0000,FFFF,H,U,,,,"MOV ?+Y, A"
D7,00,FF,H,U,,,,"MOV [?]+Y, A"
D8,00,FF,H,U,,,,"MOV ?, X"
D9,00,FF,H,U,,,,"MOV ?+Y, X"
DA,00,FF,H,U,,,,"MOVW ?, YA"
DB,00,FF,H,U,,,,"MOV ?+x, Y"
DC,,,,,,,,"DEC Y"
DD,,,,,,,,"MOV A, Y"
DE,0000,FF00,H,U,00FF,H,S,"CBNE ?+X, ^"
DF,,,,,,,,"DAA A"
E0,,,,,,,,"CLRV"
E1,,,,,,,,"TCALL 14"
E2,00,FF,H,U,,,,"SET1 ?.7"
E3,0000,FF00,H,U,00FF,H,S,"BBS ?.7, ^"
E4,00,FF,H,U,,,,"MOV A, ?"
E5,0000,FFFF,H,U,,,,"MOV A, ?"
E6,,,,,,,,"MOV A, (X)"
E7,00,FF,H,U,,,,"MOV A, [?+X]"
E8,00,FF,H,U,,,,"MOV A, #?"
E9,0000,FFFF,H,U,,,,"MOV X, ?"
EA,0000,FF1F,H,U,00E0,D,U,"NOT1 ?.^"
EB,00,FF,H,U,,,,"MOV Y, ?"
EC,0000,FFFF,H,U,,,,"MOV Y, ?"
ED,,,,,,,,"NOTC"
EE,,,,,,,,"POP Y"
EF,,,,,,,,"SLEEP"
F0,00,FF,H,S,,,,"BEQ ?"
F1,,,,,,,,"TCALL 15"
F2,00,FF,H,U,,,,"CLR1 ?.7"
F3,0000,FF00,H,U,00FF,H,S,"BBC ?.7, ^"
F4,00,FF,H,U,,,,"MOV A, ?+X"
F5,0000,FFFF,H,U,,,,"MOV A, ?+X"
F6,0000,FFFF,H,U,,,,"MOV A, ?+Y"
F7,00,FF,H,U,,,,"MOV A, [?]+Y"
F8,00,FF,H,U,,,,"MOV X, ?"
F9,00,FF,H,U,,,,"MOV X, ?+Y"
FA,0000,FF00,H,U,00FF,H,U,"MOV ^, ?"
FB,00,FF,H,U,,,,"MOV Y, ?+x"
FC,,,,,,,,"INC Y"
FD,,,,,,,,"MOV Y, A"
FE,00,FF,H,S,,,,"DBNZ Y, ?"
FF,,,,,,,,"STOP"
25 changes: 13 additions & 12 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ I came across HxD while looking for a good hex editor, to allow visually compari
I was immediately impressed that Maël had included support for Motorola S-record files, and when I noticed the Data inspector included x86 Disassembly I immediately thought how useful 6809 Disassembly would be.
As I was seeing byte differences in my 6809 ROM comparisons, I was having to manually identify what the code differences were.

I initially looked for a pre-written Disassembler that I could integrate via Maël's published plugin framework: https://github.com/maelh/hxd-plugin-framework
I initially looked for a pre-written Disassembler that I could integrate via Maël's published plugin framework: https://github.com/maelh/hxd-plugin-framework

But I quickly came to the conclusion that there wasn't really anything substantial that I could (relatively easily) migrate for this purpose.
Plus, with my retro CPU interests, I could see that I'd potentially want to also add 6800 and 6502 code disassembly (ed. which I have now done), and maybe even 68000, and looking at existing disassemblers, I really didn't like the "hard-coded" processor specific parsing approach.
Expand All @@ -31,7 +31,7 @@ I've now also added several other processor definition files including 6502 fami
To assist with debugging your own definition .csv files (or any changes you might want to make), the .ini file provides for a log file to be enabled. This provides visibility of the .csv file parsing and format errors (typos?) that are identified.

Note that while this implementation provides great flexibility for adding additional CPU Disassembly support, it's target audience is retro microprocessors. These generally have relatively simple instruction sets and addressing modes, which the definition files easily cater for.
However, I suspect limitation may be found if attempting to define more advanced / modern ISA's. Specifically, where a CPU has a significantly more complex instruction set, resulting in an excessively large number of resulting possible opcode + operand combinations.
However, I suspect limitation may be found if attempting to define more advanced / modern ISA's. Specifically, where a CPU has a significantly more complex instruction set, resulting in an excessively large number of resulting possible opcode + operand combinations.

## Installation

Expand All @@ -53,17 +53,17 @@ The .csv definition files (configured and referenced from the .ini file), have r

## CSV file column descriptions

- OpcodeBytes: The fixed (static) bytes, specified in Hex, that comprise each unique instruction Opcode.
- OpcodeBytes: The fixed (static) bytes, specified in Hex, that comprise each unique instruction Opcode.
- OperandBytes: Any additional Hex Bytes that make up the full instruction and contain the instruction Operand(s). Multi-byte Operands are specified in the byte sequence that they appear in memory. The extracted Operand(s) will however respect the target CPU's Endianness (specified in the .ini file).
- FirstOperandMask: The Hex bit mask that identifies the first Operand to be extracted from the Operand Bytes.
- FirstOperandMask: The Hex bit mask that identifies the first Operand to be extracted from the Operand Bytes.
- FirstOperandHexDec: Determines if the extracted first Operand should be rendered in Hex or Decimal format.
- FirstOperandSignedUnsigned: Determines if the extracted first Operand should be treated as a Signed or Unsigned value. Typically, Signed is used for Relative reference Operands.
- SecondOperandMask: As for FirstOperandMask, this is the Hex bit mask that identifies any required second Operand to be extracted from the Operand Bytes.
- SecondOperandMask: As for FirstOperandMask, this is the Hex bit mask that identifies any required second Operand to be extracted from the Operand Bytes.
- SecondOperandHexDec: As above for the first Operand, this determines if any extracted second Operand should be rendered in Hex or Decimal format.
- FirstOperandSignedUnsigned: As above for the first Operand, this determines if any extracted second Operand should be treated as a Signed or Unsigned value.
- AssemblyString: The Disassembled instruction string that is to be rendered in the HxD data inspector. The .ini file specifies first and second Operand wildcard characters (or strings), which you include to identify where the extracted / formatted Operand(s) should be substituted into the string.
- AssemblyString: The Disassembled instruction string that is to be rendered in the HxD data inspector. The .ini file specifies first and second Operand wildcard characters (or strings), which you include to identify where the extracted / formatted Operand(s) should be substituted into the string.

Reviewing the above, in combination with the various included (completed) .csv files, should help clarify the definition file structure.
Reviewing the above, in combination with the various included (completed) .csv files, should help clarify the definition file structure.

## Features

Expand All @@ -77,7 +77,7 @@ Reviewing the above, in combination with the various included (completed) .csv f

- Configurable, per instruction Operand, for rendering each Operand value in either Hex or Decimal format.

- Supports up to 32,767 unique instruction definitions per CPU definition file.
- Supports up to 32,767 unique instruction definitions per CPU definition file.

## CPU ISA's currently defined (Complete), or in progress (Incomplete)

Expand All @@ -87,22 +87,23 @@ Reviewing the above, in combination with the various included (completed) .csv f
- Western Design Center (WDC) W65C02S 8-bit CPU (DasmW65C02S.csv) - Complete
- Western Design Center (WDC) 65C816 8/16-bit CPU (Dasm65C816.csv) - Complete
- Motorola MC6809 8/16-bit CPU (Dasm6809.csv) - Complete
- Sony SPC700 8-bit CPU - Complete (contributed by exodustx0)

All the Complete definitions have been carefully checked, however if you identify any coding errors please raise an issue so these can be corrected.

Of Note:
- Currently only the W65C02S and 65C816 definitions include instructions having two Operands.
- Currently the MC6809 is the most complex definition, due to it's comprehensive addressing modes and extended multiple-byte opcodes. The MC6809 definition includes 5,530 unique instructions. For comparison the MC6800 has only 197 unique instruction definitions, or the simplest MOS 6502 which requires only 151 unique instruction definitions.
- Currently only the W65C02S, 65C816 and SPC700 definitions include instructions having two Operands.
- Currently the MC6809 is the most complex definition, due to it's comprehensive addressing modes and extended multiple-byte opcodes. The MC6809 definition includes 5,530 unique instructions. For comparison the MC6800 has only 197 unique instruction definitions, or the simplest MOS 6502 which requires only 151 unique instruction definitions.

## Source

The fully commented source code is available in the src folder (for those interested). Note that the source code is not required for using this HxD DataInsepctor Plugin (the required compiled .dll is in the Win64 or Win32 folder), nor is it required for adding your own .csv CPU definitions (if you do create an additional CPU defintion file, please share it!).

The source code was compiled with Delphi 10.3 Community Edition. The Community Edition is available free for non-profit use, however please refer to the Embarcadero website for their full license terms and to obtain the Delphi IDE.
The source code was compiled with Delphi 10.3 Community Edition. The Community Edition is available free for non-profit use, however please refer to the Embarcadero website for their full license terms and to obtain the Delphi IDE.

## License

HxD Plugin Framework is Copyright (C) 2019-2021 Maël Hörz. The plugin framework is licensed under the MPL.
HxD Plugin Framework is Copyright (C) 2019-2021 Maël Hörz. The plugin framework is licensed under the MPL.

This Disassembly Plugin is Copyright (C) 2021 DigicoolThings (Digicool Things), and distributed as per the MPL Larger Work definition and [licensed under the Apache License 2.0](LICENSE)

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