Merge branch 'master' into i5365-SVE-enabled-AArch64-tests

api/docs/bt.dox

@@ -382,7 +382,7 @@ execution time that affects efficiency.
 Through the basic block creation event, registered via
 dr_register_bb_event(), the client has the ability to inspect and transform
 any piece of code prior to its execution.  The client's hook receives
-three parameters:
+five parameters:
 
 \code
 dr_emit_flags_t new_block(void *drcontext, void *tag, instrlist_t *bb,
@@ -545,7 +545,7 @@ dr_emit_flags_t new_trace(void *drcontext, void *tag, instrlist_t *trace,
 
  - \c tag is a unique identifier for the trace fragment.
 
- - \c bb is a pointer to the list of instructions that comprise the
+ - \c trace is a pointer to the list of instructions that comprise the
    trace.  Clients can examine, manipulate, or completely replace the
    instructions in the list.
 

core/arch/arch.h

@@ -184,7 +184,6 @@ mixed_mode_enabled(void)
 #    define SCRATCH_REG4_OFFS REG4_OFFSET
 #    define SCRATCH_REG5_OFFS REG5_OFFSET
 #    define REG_OFFSET(reg) (X0_OFFSET + ((reg)-DR_REG_X0) * sizeof(reg_t))
-/* FIXME i#3544: Check is T6 safe to use */
 #    define CALL_SCRATCH_REG DR_REG_T6
 #    define MC_IBL_REG a2
 #    define MC_RETVAL_REG a0

core/arch/proc_shared.c

@@ -1,5 +1,5 @@
 /* **********************************************************
- * Copyright (c) 2013-2022 Google, Inc.  All rights reserved.
+ * Copyright (c) 2013-2023 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2008 VMware, Inc.  All rights reserved.
  * **********************************************************/
 
@@ -63,25 +63,36 @@
  */
 size_t cache_line_size = 32;
 static ptr_uint_t mask; /* bits that should be 0 to be cache-line-aligned */
-cpu_info_t cpu_info = { VENDOR_UNKNOWN,
+cpu_info_t cpu_info = {
+#ifdef X86
+    /* If we initialize to VENDOR_UNKNOWN we get contradictory decoding results
+     * for opcodes that vary between VENDOR_AMD and VENDOR_INTEL (because some
+     * of our decoding code checks one and some checks the other) so we pick one
+     * for a stable self-consistent default.
+     */
+    VENDOR_INTEL,
+#else
+    VENDOR_UNKNOWN,
+#endif
 #ifdef AARCHXX
-                        0,
-                        0,
+    0,
+    0,
 #endif
-                        0,
-                        0,
-                        0,
-                        0,
-                        CACHE_SIZE_UNKNOWN,
-                        CACHE_SIZE_UNKNOWN,
-                        CACHE_SIZE_UNKNOWN,
+    0,
+    0,
+    0,
+    0,
+    CACHE_SIZE_UNKNOWN,
+    CACHE_SIZE_UNKNOWN,
+    CACHE_SIZE_UNKNOWN,
 #if defined(RISCV64)
-                        /* FIXME i#3544: Not implemented */
-                        { 0 },
+    /* FIXME i#3544: Not implemented */
+    { 0 },
 #else
-                        { 0, 0, 0, 0 },
+    { 0, 0, 0, 0 },
 #endif
-                        { 0x6e6b6e75, 0x006e776f } };
+    { 0x6e6b6e75, 0x006e776f }
+};
 
 void
 proc_set_cache_size(uint val, uint *dst)

core/arch/riscv64/mangle.c

@@ -223,8 +223,26 @@ insert_reachable_cti(dcontext_t *dcontext, instrlist_t *ilist, instr_t *where,
                      byte *encode_pc, byte *target, bool jmp, bool returns, bool precise,
                      reg_id_t scratch, instr_t **inlined_tgt_instr)
 {
-    /* FIXME i#3544: Not implemented */
-    ASSERT_NOT_IMPLEMENTED(false);
+    /* A scratch register is required for holding the jump target. */
+    ASSERT(scratch != REG_NULL);
+
+    /* Load target into scratch register. */
+    insert_mov_immed_ptrsz(dcontext,
+                           (ptr_int_t)PC_AS_JMP_TGT(dr_get_isa_mode(dcontext), target),
+                           opnd_create_reg(scratch), ilist, where, NULL, NULL);
+
+    /* Even if it's a call, if it doesn't return, we use jump. */
+    if (!jmp && returns) {
+        /* jalr ra, 0(scratch) */
+        PRE(ilist, where, XINST_CREATE_call_reg(dcontext, opnd_create_reg(scratch)));
+    } else {
+        /* jalr zero, 0(scratch) */
+        PRE(ilist, where, XINST_CREATE_jump_reg(dcontext, opnd_create_reg(scratch)));
+    }
+
+    /* Always use an indirect branch for RISC-V. */
+    /* XXX i#3544: JAL can target a ±1 MiB range, can we use it for a better performance?
+     */
     return false;
 }
 

core/arch/x86/proc.c

@@ -1,5 +1,5 @@
 /* **********************************************************
- * Copyright (c) 2013-2022 Google, Inc.  All rights reserved.
+ * Copyright (c) 2013-2023 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2008 VMware, Inc.  All rights reserved.
  * **********************************************************/
 
@@ -333,6 +333,21 @@ get_processor_specific_info(void)
         our_cpuid((int *)&cpu_info.brand_string[4], 0x80000003, 0);
         our_cpuid((int *)&cpu_info.brand_string[8], 0x80000004, 0);
     }
+
+    if (standalone_library) {
+        /* For separate decoding, keep a base default and do not target the
+         * underlying processor (xref i#431, i#6420, i#5725).
+         * The user can use proc_set_vendor() to override.
+         * This affects various decoding corner cases and is important to set.
+         * We leave all the other cache info, etc. pointing to the current hardware.
+         * We set this at the end here to avoid errors in getting other
+         * cpuid values with the wrong magic parameters.
+         * XXX: This is still potentially fragile; should the decoder have
+         * a separate vendor value?
+         */
+        LOG(GLOBAL, LOG_TOP, 1, "For standalone decoding, assuming Intel target.\n");
+        cpu_info.vendor = VENDOR_INTEL;
+    }
 }
 
 /* arch specific proc info */

core/unix/signal.c

@@ -6422,15 +6422,15 @@ execute_handler_from_dispatch(dcontext_t *dcontext, int sig)
         mcontext->lr = (reg_t)dynamorio_sigreturn;
 #elif defined(RISCV64)
     /* FIXME i#3544: Check if xsp is cast correctly? */
-    sc->SC_A0 = sig;
+    mcontext->a0 = sig;
     if (IS_RT_FOR_APP(info, sig)) {
-        sc->SC_A1 = (reg_t) & ((sigframe_rt_t *)xsp)->info;
-        sc->SC_A2 = (reg_t) & ((sigframe_rt_t *)xsp)->uc;
+        mcontext->a1 = (reg_t) & ((sigframe_rt_t *)xsp)->info;
+        mcontext->a2 = (reg_t) & ((sigframe_rt_t *)xsp)->uc;
     }
     if (sig_has_restorer(info, sig))
-        sc->SC_RA = (reg_t)info->sighand->action[sig]->restorer;
+        mcontext->ra = (reg_t)info->sighand->action[sig]->restorer;
     else
-        sc->SC_RA = (reg_t)dynamorio_sigreturn;
+        mcontext->ra = (reg_t)dynamorio_sigreturn;
 #endif
 #ifdef X86
     /* Clear eflags DF (signal handler should match function entry ABI) */

suite/tests/runcmp.cmake

@@ -111,5 +111,18 @@ if (lists_identical)
 endif (lists_identical)
 
 if (NOT lists_identical)
-  message(FATAL_ERROR "failed to match expected output")
+  find_program(DIFF_CMD diff)
+  if (DIFF_CMD)
+    # Detected diff command, print a full diff for better debugging.
+    list(JOIN output "" output)
+    list(JOIN filtered_expect "" filtered_expect)
+    set(tmp "${cmp}-out")
+    set(tmp2 "${cmp}-expect")
+    file(WRITE "${tmp}" "${output}")
+    file(WRITE "${tmp2}" "${filtered_expect}")
+    execute_process(COMMAND ${DIFF_CMD} ${tmp} ${tmp2}
+      OUTPUT_VARIABLE dcmd_out)
+    message(STATUS "diff: ${dcmd_out}")
+  endif ()
+  message(FATAL_ERROR "failed to match expected output.")
 endif ()