i#1569 AArch64: Make AArch64 build.

It builds, but binaries are non-functional as many things are not yet implemented. Review-URL: https://codereview.appspot.com/293720043
DynamoRIO · Mar 11, 2016 · c2ecca2 · c2ecca2
1 parent 7136156
commit c2ecca2
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Showing 45 changed files with 581 additions and 338 deletions.
diff --git a/api/samples/CMakeLists.txt b/api/samples/CMakeLists.txt
@@ -206,11 +206,13 @@ configure_DynamoRIO_global(OFF ON)
 
 # Use ;-separated lists for source files and extensions.
 
-add_sample_client(bbbuf       "bbbuf.c"         "drmgr;drreg")
+if (NOT AARCH64) # FIXME i#1569: port to AArch64
+  add_sample_client(bbbuf       "bbbuf.c"         "drmgr;drreg")
+endif ()
 add_sample_client(bbsize      "bbsize.c"        "drmgr")
 add_sample_client(empty       "empty.c"         "")
 add_sample_client(memtrace_simple "memtrace_simple.c;utils.c" "drmgr;drutil;drx")
-if (NOT ARM) # FIXME i#1551: port to ARM
+if (X86) # FIXME i#1551, i#1569: port to ARM and AArch64
   add_sample_client(bbcount     "bbcount.c"       "drmgr;drreg")
   add_sample_client(cbr         "cbr.c"           "drmgr")
   add_sample_client(countcalls  "countcalls.c"    "")
@@ -227,13 +229,15 @@ if (NOT ARM) # FIXME i#1551: port to ARM
   add_sample_client(instrcalls  "instrcalls.c;utils.c"  "drmgr;drsyms;drx")
   # dr_insert_cbr_instrument_ex is NYI
   add_sample_client(cbrtrace    "cbrtrace.c;utils.c"    "drx")
-endif (NOT ARM)
+endif (X86)
 add_sample_client(wrap        "wrap.c"          "drmgr;drwrap")
 add_sample_client(signal      "signal.c"        "drmgr")
 add_sample_client(syscall     "syscall.c"       "drmgr")
 add_sample_client(inline      "inline.c"        "")
 add_sample_client(inscount    "inscount.c"      "drmgr")
-add_sample_client(opcodes     "opcodes.c"       "drx")
+if (NOT AARCH64) # FIXME i#1569: port to AArch64
+  add_sample_client(opcodes     "opcodes.c"       "drx")
+endif ()
 add_sample_client(stl_test    "stl_test.cpp"    "")
 # add utils.h for installation  # NON-PUBLIC
 set(srcs ${srcs} "utils.h")     # NON-PUBLIC

diff --git a/core/arch/arch.c b/core/arch/arch.c
@@ -417,7 +417,7 @@ shared_gencode_emit(generated_code_t *gencode _IF_X86_64(bool x86_mode))
     gencode->do_syscall = pc;
     pc = emit_do_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return,
                          true/*shared*/, 0, &gencode->do_syscall_offs);
-# ifdef ARM
+# if defined(ARM) || defined(AARCH64)
     /* ARM has no thread-private gencode, so our clone syscall is shared */
     gencode->do_clone_syscall = pc;
     pc = emit_do_clone_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return,
@@ -559,7 +559,7 @@ shared_gencode_init(IF_X86_64_ELSE(gencode_mode_t gencode_mode, void))
     protect_generated_code(gencode, READONLY);
 }
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 /* Called during a reset when all threads are suspended */
 void
 arch_reset_stolen_reg(void)
@@ -570,6 +570,9 @@ arch_reset_stolen_reg(void)
      */
     dr_isa_mode_t old_mode;
     dcontext_t *dcontext;
+#ifdef AARCH64
+    ASSERT_NOT_IMPLEMENTED(false); /* FIXME i#1569 */
+#endif
     if (DR_REG_R0 + INTERNAL_OPTION(steal_reg_at_reset) == dr_reg_stolen)
         return;
     SYSLOG_INTERNAL_INFO("swapping stolen reg from %s to %s",
@@ -595,6 +598,9 @@ arch_reset_stolen_reg(void)
 void
 arch_mcontext_reset_stolen_reg(dcontext_t *dcontext, priv_mcontext_t *mc)
 {
+#ifdef AARCH64
+    ASSERT_NOT_IMPLEMENTED(false); /* FIXME i#1569 */
+#endif
     /* Put the app value in the old stolen reg */
     *(reg_t*)(((byte *)mc) +
               opnd_get_reg_dcontext_offs(DR_REG_R0 + INTERNAL_OPTION(steal_reg))) =
@@ -664,7 +670,7 @@ arch_init(void)
     ASSERT(syscall_method != SYSCALL_METHOD_UNINITIALIZED);
 #endif
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
     dr_reg_stolen = DR_REG_R0 + DYNAMO_OPTION(steal_reg);
     ASSERT(dr_reg_stolen >= DR_REG_STOLEN_MIN && dr_reg_stolen <= DR_REG_STOLEN_MAX)
 #endif
@@ -1104,7 +1110,7 @@ arch_thread_init(dcontext_t *dcontext)
     return;
 #endif
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
     /* Store addresses we access via TLS from exit stubs and gencode. */
     get_local_state_extended()->spill_space.fcache_return =
         PC_AS_JMP_TGT(isa_mode, fcache_return_shared_routine());
@@ -2837,7 +2843,7 @@ hook_vsyscall(dcontext_t *dcontext)
     instr_free(dcontext, &instr);
     return res;
 # undef CHECK
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
     /* No vsyscall support needed for our ARM targets */
     ASSERT_NOT_REACHED();
     return false;
@@ -2870,7 +2876,7 @@ unhook_vsyscall(void)
         ASSERT(res);
     }
     return true;
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
     ASSERT_NOT_IMPLEMENTED(get_syscall_method() != SYSCALL_METHOD_SYSENTER);
     return false;
 #endif /* X86/ARM */
@@ -2892,7 +2898,7 @@ check_syscall_method(dcontext_t *dcontext, instr_t *instr)
     else if (instr_get_opcode(instr) == OP_call_ind)
         new_method = SYSCALL_METHOD_WOW64;
 # endif
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
     if (instr_get_opcode(instr) == OP_svc)
         new_method = SYSCALL_METHOD_SVC;
 #endif /* X86/ARM */
@@ -3262,7 +3268,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml)
                , context->r8,  context->r9,  context->r10,  context->r11,
                context->r12, context->r13, context->r14,  context->r15
 # endif /* X64 */
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
                context->r0,  context->r1,  context->r2,  context->r3,
                context->r4,  context->r5,  context->r6,  context->r7,
                context->r8,  context->r9,  context->r10, context->r11,
@@ -3324,7 +3330,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml)
                context->xflags, context->pc);
 }
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 reg_t
 get_stolen_reg_val(priv_mcontext_t *mc)
 {

diff --git a/core/arch/arch.h b/core/arch/arch.h
@@ -114,7 +114,7 @@ mixed_mode_enabled(void)
 # define SCRATCH_REG3_OFFS XDX_OFFSET
 # define SCRATCH_REG4_OFFS XSI_OFFSET
 # define SCRATCH_REG5_OFFS XDI_OFFSET
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
 # define R0_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r0)))
 # define R1_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r1)))
 # define R2_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r2)))
@@ -1291,7 +1291,7 @@ add_patch_entry_internal(patch_list_t *patch, instr_t *instr, ushort patch_flags
 cache_pc
 get_direct_exit_target(dcontext_t *dcontext, uint flags);
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 size_t
 get_fcache_return_tls_offs(dcontext_t *dcontext, uint flags);
 

diff --git a/core/arch/arch_exports.h b/core/arch/arch_exports.h
@@ -125,7 +125,7 @@ typedef struct _table_stat_state_t {
 #endif
 } table_stat_state_t;
 
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 typedef struct _ibl_entry_pc_t {
     byte *ibl;
     byte *unlinked;
@@ -140,13 +140,13 @@ typedef struct _spill_state_t {
     /* Four registers are used in the indirect branch lookup routines */
 #ifdef X86
     reg_t xax, xbx, xcx, xdx;    /* general-purpose registers */
-#elif defined (ARM)
+#elif defined (ARM) || defined(AARCH64)
     reg_t r0, r1, r2, r3;
     reg_t reg_stolen;            /* slot for the stolen register */
 #endif
     /* FIXME: move this below the tables to fit more on cache line */
     dcontext_t *dcontext;
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
     /* We store addresses here so we can load pointer-sized addresses into
      * registers with a single instruction in our exit stubs and gencode.
      */
@@ -184,7 +184,7 @@ typedef struct _local_state_extended_t {
 # define SCRATCH_REG1             DR_REG_XBX
 # define SCRATCH_REG2             DR_REG_XCX
 # define SCRATCH_REG3             DR_REG_XDX
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
 # define TLS_REG0_SLOT            ((ushort)offsetof(spill_state_t, r0))
 # define TLS_REG1_SLOT            ((ushort)offsetof(spill_state_t, r1))
 # define TLS_REG2_SLOT            ((ushort)offsetof(spill_state_t, r2))
@@ -198,7 +198,7 @@ typedef struct _local_state_extended_t {
 #define IBL_TARGET_REG           SCRATCH_REG2
 #define IBL_TARGET_SLOT          TLS_REG2_SLOT
 #define TLS_DCONTEXT_SLOT        ((ushort)offsetof(spill_state_t, dcontext))
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 # define TLS_FCACHE_RETURN_SLOT  ((ushort)offsetof(spill_state_t, fcache_return))
 #endif
 
@@ -485,7 +485,39 @@ static inline int64 atomic_add_exchange_int64(volatile int64 *var, int64 value)
 #  define SET_FLAG(cc, flag) __asm__ __volatile__("set"#cc " %0" :"=qm" (flag) )
 #  define SET_IF_NOT_ZERO(flag) SET_FLAG(nz, flag)
 #  define SET_IF_NOT_LESS(flag) SET_FLAG(nl, flag)
+
+# elif defined(AARCH64)
+
+/* FIXME i#1569: NYI */
+#  define AARCH64_NYI do { ASSERT_NOT_IMPLEMENTED(false); } while (0)
+
+#  define ATOMIC_INC_int(var) do { AARCH64_NYI; ++var; } while (0)
+#  define ATOMIC_INC_int64(var) do { AARCH64_NYI; ++var; } while (0)
+#  define ATOMIC_DEC_int(var) do { AARCH64_NYI; --var; } while (0)
+#  define ATOMIC_DEC_int64(var) do { AARCH64_NYI; --var; } while (0)
+#  define ATOMIC_ADD_int(var, val) do { AARCH64_NYI; var += val; } while (0)
+#  define ATOMIC_ADD_int64(var, val) do { AARCH64_NYI; var += val; } while (0)
+#  define ATOMIC_ADD_EXCHANGE_int(var, val, res) \
+    do { AARCH64_NYI; res = *var; *var += val; } while (0)
+#  define ATOMIC_ADD_EXCHANGE_int64(var, val, res) \
+    do { AARCH64_NYI; res = *var; *var += val; } while (0)
+#  define ATOMIC_COMPARE_EXCHANGE_int(var, compare, exchange) AARCH64_NYI
+#  define ATOMIC_COMPARE_EXCHANGE_int64(var, compare, exchange) AARCH64_NYI
+#  define ATOMIC_EXCHANGE(var, newval, result) \
+    do { AARCH64_NYI; result = var; var = newval; } while (0)
+#  define SPINLOCK_PAUSE() AARCH64_NYI
+uint64 proc_get_timestamp(void);
+#  define RDTSC_LL(llval) AARCH64_NYI
+
+#  define GET_FRAME_PTR(var) asm volatile("mov %0, x29" : "=r"(var))
+#  define GET_STACK_PTR(var) asm volatile("mov %0, sp" : "=r"(var))
+
+#  define SET_FLAG(cc, flag) do { AARCH64_NYI; flag = 0; } while (0)
+#  define SET_IF_NOT_ZERO(flag) SET_FLAG(ne, flag)
+#  define SET_IF_NOT_LESS(flag) SET_FLAG(ge, flag)
+
 # else /* ARM */
+
 #  define ATOMIC_4BYTE_WRITE(target, value, hot_patch) do {           \
      ASSERT(sizeof(value) == 4);                                      \
      /* Load and store instructions are atomic on ARM if aligned. */  \
@@ -825,7 +857,7 @@ void arch_thread_exit(dcontext_t *dcontext _IF_WINDOWS(bool detach_stacked_callb
 void arch_thread_profile_exit(dcontext_t *dcontext);
 void arch_profile_exit(void);
 #endif
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 void arch_reset_stolen_reg(void);
 void arch_mcontext_reset_stolen_reg(dcontext_t *dcontext, priv_mcontext_t *mc);
 #endif
@@ -843,7 +875,7 @@ priv_mcontext_t *dr_mcontext_as_priv_mcontext(dr_mcontext_t *mc);
 priv_mcontext_t *get_priv_mcontext_from_dstack(dcontext_t *dcontext);
 void dr_mcontext_init(dr_mcontext_t *mc);
 void dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml);
-#ifdef ARM
+#if defined(ARM) || defined(AARCH64)
 reg_t get_stolen_reg_val(priv_mcontext_t *context);
 void set_stolen_reg_val(priv_mcontext_t *mc, reg_t newval);
 #endif
@@ -1323,7 +1355,7 @@ decode_init(void);
 # define MAX_PAD_SIZE 3
 
 /****************************************************************************/
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
 
 # ifdef X64
 #  define FRAG_IS_THUMB(flags) false
@@ -1573,6 +1605,13 @@ enum {
     CTI_IAT_LENGTH     = 6, /* FF 15 38 10 80 7C call dword ptr ds:[7C801038h] */
     CTI_FAR_ABS_LENGTH = 7, /* 9A 1B 07 00 34 39 call 0739:3400071B            */
                             /* 07                                              */
+#elif defined(AARCH64)
+    MAX_INSTR_LENGTH = 4,
+    CBR_LONG_LENGTH  = 4,
+    JMP_LONG_LENGTH  = 4,
+    JMP_SHORT_LENGTH = 4,
+    CBR_SHORT_REWRITE_LENGTH = 4,
+    SVC_LENGTH = 4,
 #elif defined(ARM)
     MAX_INSTR_LENGTH = ARM_INSTR_SIZE,
     CBR_LONG_LENGTH  = ARM_INSTR_SIZE,
@@ -1946,7 +1985,9 @@ typedef struct dr_jmp_buf_t {
     reg_t r8, r9, r10, r11, r12, r13, r14, r15;
 # endif
 #elif defined(ARM) /* for arm.asm */
-    reg_t regs[IF_X64_ELSE(32, 16)/*DR_NUM_GPR_REGS*/];
+    reg_t regs[16/*DR_NUM_GPR_REGS*/];
+#elif defined(AARCH64) /* for aarch64.asm */
+    reg_t regs[22]; /* callee-save regs: X19-X30, (gap), SP, D8-D15 */
 #endif /* X86/ARM */
 #if defined(UNIX) && defined(DEBUG)
     /* i#226/PR 492568: we avoid the cost of storing this by using the