i#1569 AArch64: Use predicate for B.cond instead of second operand.

Change representation of "B.cond label" from "Bcond label, cond" to predicated "Bcond label", more similar to other architectures. Review-URL: https://codereview.appspot.com/296040043
DynamoRIO · May 3, 2016 · e9772cf · e9772cf
1 parent 5a950fd
commit e9772cf
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Showing 4 changed files with 11 additions and 12 deletions.
diff --git a/core/arch/aarch64/decode.c b/core/arch/aarch64/decode.c
@@ -101,10 +101,10 @@ decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
     }
     else if ((enc & 0xff000010) == 0x54000000) {
         instr_set_opcode(instr, OP_bcond);
-        instr_set_num_opnds(dcontext, instr, 0, 2);
+        instr_set_num_opnds(dcontext, instr, 0, 1);
         instr->src0 = opnd_create_pc(pc + ((enc >> 5 & 0x3ffff) << 2) -
                                      ((enc >> 5 & 0x40000) << 2));
-        instr->srcs[0] = OPND_CREATE_INT8(enc & 15);
+        instr_set_predicate(instr, enc & 0xf);
     }
     else if ((enc & 0x7e000000) == 0x34000000) {
         instr_set_opcode(instr, TEST(1 << 24, enc) ? OP_cbnz : OP_cbz);

diff --git a/core/arch/aarch64/encode.c b/core/arch/aarch64/encode.c
@@ -121,12 +121,11 @@ static uint encode_common(byte *pc, instr_t *i)
         return (0x14000000 | (uint)(i->opcode == OP_bl) << 31 |
                 (0x3ffffff & (uint)(i->src0.value.pc - pc) >> 2));
     case OP_bcond:
-        ASSERT(i->num_dsts == 0 && i->num_srcs == 2 &&
-               i->src0.kind == PC_kind &&
-               i->srcs[0].kind == IMMED_INTEGER_kind);
+        ASSERT(i->num_dsts == 0 && i->num_srcs == 1 &&
+               i->src0.kind == PC_kind);
         return (0x54000000 |
                 (0x001fffff & (uint)(i->src0.value.pc - pc)) >> 2 << 5 |
-                (i->srcs[0].value.immed_int & 15));
+                (instr_get_predicate(i) & 0xf));
     case OP_cbnz:
     case OP_cbz:
         ASSERT(i->num_dsts == 0 && i->num_srcs == 2 &&

diff --git a/core/arch/aarch64/instr.c b/core/arch/aarch64/instr.c
@@ -247,17 +247,13 @@ instr_predicate_reads_srcs(dr_pred_type_t pred)
 bool
 instr_predicate_writes_eflags(dr_pred_type_t pred)
 {
-    ASSERT_NOT_IMPLEMENTED(false); /* FIXME i#1569 */
     return false;
 }
 
 bool
 instr_predicate_is_cond(dr_pred_type_t pred)
 {
-    /* Currently there are no predicated instructions as we treat the
-     * condition in "B.cond label" as a second operand: "B label, cond".
-     */
-    return false;
+    return pred != DR_PRED_NONE && pred != DR_PRED_AL && pred != DR_PRED_NV;
 }
 
 bool

diff --git a/core/arch/instr.h b/core/arch/instr.h
@@ -257,7 +257,7 @@ typedef enum _dr_pred_type_t {
      * unconditionally written, unlike regular destination operands.
      */
     DR_PRED_COMPLEX,
-#elif defined(ARM)
+#elif defined(ARM) || defined(AARCH64)
     DR_PRED_EQ, /**< ARM condition: 0000 Equal                   (Z == 1)           */
     DR_PRED_NE, /**< ARM condition: 0001 Not equal               (Z == 0)           */
     DR_PRED_CS, /**< ARM condition: 0010 Carry set               (C == 1)           */
@@ -273,7 +273,11 @@ typedef enum _dr_pred_type_t {
     DR_PRED_GT, /**< ARM condition: 1100 Signed greater than     (Z == 0 and N == V)*/
     DR_PRED_LE, /**< ARM condition: 1101 Signed <=               (Z == 1 or N != V) */
     DR_PRED_AL, /**< ARM condition: 1110 Always (unconditional)                    */
+# ifdef AARCH64
+    DR_PRED_NV, /**< ARM condition: 1111 Never, meaning always                     */
+# else
     DR_PRED_OP, /**< ARM condition: 1111 Part of opcode                            */
+# endif
     /* Aliases */
     DR_PRED_HS = DR_PRED_CS, /**< ARM condition: alias for DR_PRED_CS. */
     DR_PRED_LO = DR_PRED_CC, /**< ARM condition: alias for DR_PRED_CC. */