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i#5365 AArch64: Fix 0 size read/write records in drmemtrace #6544

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merged 5 commits into from
Jan 18, 2024

Commits on Jan 8, 2024

  1. i#5365 AArch64: Fix 0 size read/write records in drmemtrace

    When debugging i#6499 we noticed that drcachesim was producing 0 byte
    read/write records for some SVE load/store instructions:
    
    ```
     ifetch       4 byte(s) @ 0x0000000000405b3c a54a4681   ld1w   (%x20,%x10,lsl #2) %p1/z -> %z1.s
     read         0 byte(s) @ 0x0000000000954e80 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e84 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e88 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e8c by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e90 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e94 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e98 by PC 0x0000000000405b3c
     read         0 byte(s) @ 0x0000000000954e9c by PC 0x0000000000405b3c
     ifetch       4 byte(s) @ 0x0000000000405b4
    ```
    
    This turned out to be due to drdecode being linked into drcachesim
    twice: once into the drcachesim executable, once into libdynamorio.
    drdecode uses a global variable to store the SVE vector length to use
    when decoding so we end up with two copies of that variable and only
    one was being initialized.
    To fix this properly we would need to refactor the libraries so that
    there is only one copy of the sve_veclen global variable, or change the
    way that the decoder gets the vector length so its no longer stored in
    a global variable. In the mean time we have a workaround which
    makes sure both copies of the variable get initialized and drcachesim
    produces correct results.
    
    With that workaround in place however, the results were still wrong.
    For expanded scatter/gather instructions when you are using an offline
    trace, raw2trace doesn't have access to the load/store instructions
    from the expansion, only the original app scatter/gather instruction.
    It has to create the read/write records using only information from the
    original scatter/gather instruction and it uses the size of the memory
    operand to determine the size of each read/write. This works for x86
    because the x86 IR uses the per-element data size as for the memory
    operand of scatter/gather instructions. This doesn't work for AArch64
    because the AArch64 codec uses the maximum data transferred
    (per-element data size * number of elements) like other SIMD load/store
    instructions.
    
    We plan to make the AArch64 IR consistent with x86 by changing it to
    use the same convention as x86 for scatter/gather instructions but in
    the mean time we can work around the inconsistency by fixing the size
    in raw2trace based on the instruction's opcode.
    
    Issues: #6499, #5365
    jackgallagher-arm committed Jan 8, 2024
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  2. Fix formatting

    jackgallagher-arm committed Jan 8, 2024
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Commits on Jan 11, 2024

  1. Update issue refs

    Change-Id: Idd84efa6be879af2b12f849c2143212cb48dacc1
    jackgallagher-arm committed Jan 11, 2024
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Commits on Jan 18, 2024

  1. Merge branch 'master' into i5365-fix-drcachesim-0-size-read-write

    Change-Id: I82d48ab7fc69e485a9f92dc2d85254723bf2f51a
    jackgallagher-arm committed Jan 18, 2024
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  2. Update comment

    jackgallagher-arm committed Jan 18, 2024
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