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FPGAmaster-wyc/README.md

👀 访客数 👀

FPGAmaster-wyc :: Visitor's Count

 

🙋 Hello

🤺 About Me

  📫嗨,你好,我是FPGAmaster。

  🚀热爱编程、旅行、游戏。

  ☀️热爱FPGA和 IC 芯片事业,希望能成为一名优秀的FPGA开发者。

  🌍我们正在让这个世界变得更加美好,通过代码的重复使用和延展构建完美体系。

  🌐We're making the world a better place. Through constructing elegant hierarchies for maximum code reuse and extensibility.

 
 

 

⚡ 我的技术栈 | My Tech Stack ⚡

systemverilog verilog C Badge C++ Badge Qt Badge Python Badge Linux Badge Windows Badge

Visual Studio Code Badge GitHub Badge Visual Studio Badge Static Badge

quartus vivado

ModelSim

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  1. ov5640_HLR12-6SS ov5640_HLR12-6SS Public

    ov5640摄像头,HLR12-6SS 雷达模块

    Verilog 3

  2. LVDS_RX_DATA LVDS_RX_DATA Public

    接受LVDS数据,并输出sof,eof,sol,eol

    Verilog 1

  3. verilog_commonModule verilog_commonModule Public

    verilog通用模块,一些平常经常调用的小模块

    VHDL 1

  4. Vivado_Git_Example Vivado_Git_Example Public

    用Git管理,vivado工程的模板文件夹和tcl脚本文件

    Tcl 1

  5. XDMA_DDR_sim XDMA_DDR_sim Public

    测试写入DDR模块

    Verilog 1 1

  6. GEN_data_LVDS GEN_data_LVDS Public

    使用p701开发板,用lvds1,产生红外地平议数据

    Shell 1