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added _very_ simple AI

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1 parent 629369b commit 3b4b1d6cae019310c3a895d2d2176596581b3ea9 unknown committed Jul 19, 2009
Showing with 99 additions and 36 deletions.
  1. +27 −0 AI.vhd
  2. BIN Pong.ise
  3. +4 −1 ball.vhd
  4. +3 −1 keyboard.vhd
  5. +17 −3 process_keys.vhd
  6. +48 −31 vga.vhd
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27 AI.vhd
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity AI is
+ Port (
+ ai_enabled: in std_logic;
+ left_pos: in integer range 0 to 430;
+ left_pos_out: out integer range 0 to 430;
+ ball_pos: in integer range 0 to 480
+ );
+end AI;
+
+architecture Behavioral of AI is
+begin
+
+ process (left_pos, ball_pos, ai_enabled)
+ begin
+ if ai_enabled ='0' then
+ left_pos_out <=left_pos;
+ else
+ left_pos_out <= ball_pos;
+ end if;
+ end process;
+
+end Behavioral;
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BIN Pong.ise
Binary file not shown.
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@@ -15,7 +15,8 @@ entity ball is
rgb_out : out STD_LOGIC_VECTOR (2 downto 0);
clk25 : in bit;
reset : in bit;
- forward_game_over : out std_logic);
+ forward_game_over : out std_logic;
+ ball_y_pos_out: out integer range 0 to 480);
end ball;
architecture Behavioral of ball is
@@ -55,6 +56,8 @@ begin
clk25 => clk25,
reset => reset,
game_over => forward_game_over);
+
+ ball_y_pos_out <= y_pos; -- for AI
process (intern_rgb, x_pos, y_pos, clk25,X,Y)
begin
View
@@ -8,7 +8,7 @@ entity keyboard is
kbclk: in std_logic;
kbdata: in std_logic;
clk: in std_logic;
- keysout : out std_logic_vector(12 downto 0)
+ keysout : out std_logic_vector(13 downto 0)
);
end keyboard;
@@ -40,6 +40,7 @@ begin
when x"1E" => keysout(10) <= '0'; break_set <='0'; -- 2
when x"26" => keysout(11) <= '0'; break_set <='0'; -- 3
when x"25" => keysout(12) <= '0'; break_set <='0'; -- 4
+ when x"1C" => keysout(13) <= '0'; break_set <='0'; -- a
when x"F0" => break_set <= '1'; break_set <='0';
when others => break_set <='0';
end case;
@@ -59,6 +60,7 @@ begin
when x"1E" => keysout(10) <= '1';
when x"26" => keysout(11) <= '1';
when x"25" => keysout(12) <= '1';
+ when x"1C" => keysout(13) <= '1';
when others =>
end case;
end if;
View
@@ -5,24 +5,27 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity process_keys is
port (
- keys_in : in std_logic_vector(12 downto 6);
+ keys_in : in std_logic_vector(13 downto 6);
reset: in bit;
game_over: in std_logic;
clk25: in bit;
hold_out: out std_logic;
inverse_out: out bit;
- ballspeed_out : out bit_vector(1 downto 0);
- paddlespeed_out : out bit
+ ballspeed_out : out std_logic_vector(1 downto 0);
+ paddlespeed_out : out bit;
+ AI_out: out std_logic
);
end process_keys;
architecture Behavioral of process_keys is
signal set_pause_key: std_logic :='0';
signal set_inverse_key: std_logic := '0';
signal set_paddlespeed_key: std_logic :='0';
+ signal set_AI_key: std_logic := '0';
signal Q_hold: std_logic := '1';
signal Q_inverse: bit := '0';
signal Q_paddlespeed: bit := '0';
+ signal Q_AI: std_logic := '0';
begin
pause_key: process (clk25)
@@ -48,6 +51,17 @@ begin
end if;
end process inverse_key;
+ ai_key: process (clk25)
+ begin
+ if clk25'event and clk25='1' then
+ if keys_in(13)='1' and set_inverse_key ='0' then
+ Q_AI <= not (Q_AI);
+ set_AI_key <= '1';
+ elsif set_AI_key ='1' and keys_in(13)='0' then set_AI_key <= '0'; end if;
+ AI_out <= Q_AI;
+ end if;
+ end process ai_key;
+
ballspeed_keys: process(keys_in(12 downto 9), clk25)
begin
if clk25'event and clk25='1' then
View
79 vga.vhd
@@ -19,20 +19,21 @@ architecture Behavioral of vga is
kbclk: in std_logic;
kbdata: in std_logic;
clk: in std_logic;
- keysout : out std_logic_vector(12 downto 0)
+ keysout : out std_logic_vector(13 downto 0)
);
end component;
component process_keys
port (
- keys_in : in std_logic_vector(12 downto 6);
+ keys_in : in std_logic_vector(13 downto 6);
reset: in bit;
game_over: in std_logic;
clk25: in bit;
hold_out: out std_logic;
inverse_out: out bit;
- ballspeed_out : out bit_vector(1 downto 0);
- paddlespeed_out : out bit
+ ballspeed_out : out std_logic_vector(1 downto 0);
+ paddlespeed_out : out bit;
+ AI_out: out std_logic
);
end component;
@@ -86,19 +87,19 @@ architecture Behavioral of vga is
end component;
component ball is
- Port (
- speed : in bit_vector (1 downto 0);
- hold : in std_logic;
- bar_left : in integer range 0 to 430;
- bar_right : in integer range 0 to 430;
- ball_out : out bit;
- X : in integer range 0 to 640;
- Y : in integer range 0 to 480;
- rgb_in : in STD_LOGIC_VECTOR (2 downto 0);
- rgb_out : out STD_LOGIC_VECTOR (2 downto 0);
- clk25 : in bit;
- reset : in bit;
- forward_game_over : out std_logic);
+ Port ( speed : in std_logic_vector (1 downto 0);
+ hold : in std_logic;
+ bar_left : in integer range 0 to 430;
+ bar_right : in integer range 0 to 430;
+ X : in integer range 0 to 640;
+ Y : in integer range 0 to 480;
+ ball_out : out bit;
+ rgb_in : in STD_LOGIC_VECTOR (2 downto 0);
+ rgb_out : out STD_LOGIC_VECTOR (2 downto 0);
+ clk25 : in bit;
+ reset : in bit;
+ forward_game_over : out std_logic;
+ ball_y_pos_out: out integer range 0 to 480);
end component;
component ball_out_handler is
@@ -107,8 +108,17 @@ architecture Behavioral of vga is
rgb_out: out STD_LOGIC_VECTOR (2 downto 0);
clk25 : in bit);
end component;
+
+ component AI is
+ Port (
+ ai_enabled: in std_logic;
+ left_pos: in integer range 0 to 430;
+ left_pos_out: out integer range 0 to 430;
+ ball_pos: in integer range 0 to 480
+ );
+ end component;
- signal intermediate_bar_left : integer range 0 to 430;
+ signal intermediate_bar_left : integer range 0 to 430; -- to AI
signal intermediate_bar_right : integer range 0 to 430;
signal intermediate_ball_out : bit;
signal intermediate_X : integer range 0 to 640;
@@ -120,13 +130,16 @@ architecture Behavioral of vga is
signal intermediate_rgb3 : STD_LOGIC_VECTOR (2 downto 0); -- balken
signal intermediate_rgb4 : STD_LOGIC_VECTOR (2 downto 0); -- ball
signal intermediate_rgb5 : STD_LOGIC_VECTOR (2 downto 0); -- game over
- signal intermediate_keys : STD_LOGIC_VECTOR (12 downto 0);
+ signal intermediate_keys : STD_LOGIC_VECTOR (13 downto 0);
signal intermediate_reset : bit;
signal intermediate_hold: std_logic;
signal intermediate_inverse: bit;
signal intermediate_game_over: std_logic;
- signal intermediate_ballspeed: bit_vector (1 downto 0);
+ signal intermediate_ballspeed: std_logic_vector (1 downto 0);
signal intermediate_paddlespeed: bit;
+ signal intermediate_ballpos : integer range 0 to 480;
+ signal intermediate_ai_enabled : std_logic;
+ signal intermediate_bar_left2 : integer range 0 to 430; --after AI
begin
@@ -153,14 +166,15 @@ begin
keysout => intermediate_keys);
verarbeite_keys : process_keys port map (
- keys_in => intermediate_keys(12 downto 6),
+ keys_in => intermediate_keys(13 downto 6),
reset => intermediate_reset,
game_over => intermediate_game_over,
clk25 => intermediate_clk25,
hold_out => intermediate_hold,
inverse_out => intermediate_inverse,
ballspeed_out => intermediate_ballspeed,
- paddlespeed_out => intermediate_paddlespeed);
+ paddlespeed_out => intermediate_paddlespeed,
+ AI_out => intermediate_ai_enabled);
sigTime : SignalTiming port map (
hsync => intermediate_hsync,
@@ -194,10 +208,17 @@ begin
clk25 => intermediate_clk25,
reset => intermediate_reset);
+ KI : AI port map (
+ ai_enabled => intermediate_ai_enabled,
+ left_pos => intermediate_bar_left,
+ left_pos_out => intermediate_bar_left2,
+ ball_pos => intermediate_ballpos
+ );
+
male_ball : ball port map (
speed => intermediate_ballspeed (1 downto 0),
hold => intermediate_hold,
- bar_left => intermediate_bar_left,
+ bar_left => intermediate_bar_left2,
bar_right => intermediate_bar_right,
ball_out => intermediate_ball_out,
X => intermediate_X,
@@ -206,7 +227,8 @@ begin
rgb_out => intermediate_rgb4,
clk25 => intermediate_clk25,
reset => intermediate_reset,
- forward_game_over => intermediate_game_over);
+ forward_game_over => intermediate_game_over,
+ ball_y_pos_out => intermediate_ballpos);
ball_out_inverse : ball_out_handler port map (
ball_out => intermediate_ball_out,
@@ -221,13 +243,8 @@ begin
rgb_out => global_rgb
);
--- process (intermediate_clk25)
--- begin
--- if intermediate_clk25'event and intermediate_clk25='1' then
- global_hsync <= intermediate_hsync;
- global_vsync <= intermediat_vsync;
--- end if;
--- end process;
+ global_hsync <= intermediate_hsync;
+ global_vsync <= intermediat_vsync;
end Behavioral;

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