This repository contains all the RTL designs I have implemented in Quartus Prime.
Day 1- Half Adder using Data FLow Model
Day 2- Full Adder Uisng Data Flow Model
Day 3 - 4 Bit Adder
Day 4 - Mux 4:1 using Behavioral Model
Day 5 - D flip flop (Synchronous)
Day 6 - 3:8 Decoder
Day 7 - 8:3 Encoder